Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 788

Table 3-1.
PSR Bit
be
ic & i
bn
dt, rt, it, pk
dfl & dfh
mfl, mfh
pp
up
sp
di
si
ac
db, lp, tb, ss
cpl
is
id, da, ia, dd, ed
ri
mc
RSE.CFLE
(not a PSR bit)
3.3.2 Interruption Register State
The Itanium architecture provides a set of hardware registers which, if interruption
collection is enabled, capture relevant interruption state when an interruption occurs.
The state of the PSR.ic bit at the time of an interruption controls whether collection is
enabled. In this section, it is assumed that interruption collection is enabled (PSR.ic is
1); see Section 3.4.3, "Nested Interruptions" on page 2:546
interruptions when collection is disabled (PSR.ic is 0). For details on collection of
interruption resources for each interruption vector refer to
Vector Descriptions"
2:540
Interruption Handler Execution Environment (PSR and RSE.CFLE
Settings)
New Value
DCR.be Byte order used by handler is determined by be-bit in DCR register.
0 Disables interruption collection and external interrupts. Bank 0 is
made active bank. This is discussed above
0
unchanged Instruction/Data/RSE address translation and protection key setting
remain unchanged.
0 Floating-point registers are made accessible. This allows handlers
to spill FP registers without having to toggle FP disable bits first.
unchanged
Modified bits indicate which registers were touched. See
Section 4.2.2, "Preservation of Floating-point State in the OS" on
page 2:553
DCR.pp Privileged Monitoring is determined by pp-bit in DCR register. By
default, user counters are enabled and performance monitors are
unchanged
unsecured in handlers. See
Support"
0
0 Instruction set transitions are not intercepted.
0 Interval timer is unsecured.
0 No alignment checks are performed.
0 Debug breakpoints, lower-privilege interception, taken branch and
single step trapping are disabled.
0 Current privilege level becomes most privileged.
0 Intel Itanium Instruction set. Handlers execute Intel Itanium
instructions.
0 Instruction/data debug, access bit and speculation deferral bits are
disabled. For details, refer to
Suppression" on page 2:104
Speculative Load Faults" on page
0 Interrupt handler starts at first instruction is bundle.
unchanged Software can mask delivery of some machine check conditions by
setting PSR.mc to 1, but the processor hardware does not set this
bit upon delivery of an IVA-based interruption. Delivery of resets
and BINITs cannot be masked.
0 Allows interruption handler to service faults in presence of an
incomplete current register stack frame. This can happen when a
mandatory RSE load takes an exception during when RSE is
servicing a register stack underflow. For details refer to
"RSE Interruptions" on page
and Chapter 9, "IA-32 Interruption Vector Descriptions."
Effect on Low-level Interruption Handler
for details.
Chapter 12, "Performance Monitoring
for details.
Section 5.5.4, "Single Instruction Fault
and Section 5.5.5, "Deferral of
2:105.
2:144.
for details on handling
Chapter 8, "Interruption
Volume 2, Part 2: Interruptions and Serialization
Section 6.6,