Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 634

PAL_CACHE_WRITE
Table 11-77. part Input Values
Value
0 data
1 tag
2 data protection
3 tag protection
4 combined data and tag protection
All other values of part are reserved.
• mesi
–
or dirty, shared or exclusive. Though there may be multiple calls to
PAL_CACHE_WRITE to the same cache line, the last call's mesi will be in effect.
Values are defined as follows:
Table 11-78. mesi Return Values
Value
0 invalid
1 shared
2 exclusive
3 modified
All other values of mesi are reserved.
• start
–
invert. If length is 0 or part is not 0 or 1, this field is ignored.
• length
no bits are inverted and start is ignored. If part is not 0 or 1, this field is ignored.
• trigger
procedure. If trigger is 0, the procedure writes data and returns. If trigger is 1 and
cache_type is data/unified, the procedure writes data and executes a 64-bit load
from address before returning. If trigger is 1 and cache_type is set to instruction,
the procedure writes data and branches to the address. All other values are
reserved.
The data argument contains the value to write into the cache. Its contents are
interpreted based on the part field as follows:
Table 11-79. Interpretation of data Input Field
Part
0 64-bit data to write to the specified line (with optional bit field inversion).
1 right-justified tag to write into the specified line (with optional bit field inversion).
2 right-justified protection bits corresponding to the 64 bits of data at address. If the cache uses less
than 64-bits of data to generate protection, data will contain more than one value. For example if a
cache generates parity for every 8-bits of data, this return value would contain 8 parity values. The
PAL_CACHE_PROT_INFO call returns information on how a cache generates protection
information in order to decode this return value. If a cache uses greater than 64-bits of data to
generate protection, data will contain the value to use for the portion of the cache line indicated by
address.
3 right-justified protection bits for the cache line tag.
4 right-justified protection bits for the cache line tag and 64 bits of data at address.
2:386
Description
Unsigned 8-bit integer denoting whether the line should be written as clean
Description
Unsigned 8-bit integer denoting the least-significant bit of the field in data to
Unsigned 8-bit integer denoting the number of bits to invert. If length is 0,
–
Unsigned 8-bit integer denoting whether to trigger the error while in
–
Data
Volume 2, Part 1: Processor Abstraction Layer