Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 737

PAL_VPS_RESUME_NORMAL – Resume Virtual Processor Normal
(0x0000)
Resumes the current virtual processor. This service is used when vpsr.ic is 1. This
Purpose:
service can also be used independent of the state of vpsr.ic if all virtualization
accelerations and disables are disabled.
Arguments:
Argument
GR24
GR25
GR26
GR27
GR28
GR29
GR30
GR31
PAL_VPS_RESUME_NORMAL does not return to the VMM.
Returns:
On interruptions or intercepts, PAL_VPS_RESUME_NORMAL allows the VMM to resume
Description:
the same virtual processor where the vpsr.ic is 1. PAL_VP_RESTORE can be used to
restore the state of a different virtual processor.
The VMM specifies the VBR0 of the virtual processor in GR24 and the 64-bit virtual
pointer to the VPD in GR25.
The VMM is responsible for setting up all the required virtual processor state in the
architectural registers as well as in the VPD prior to invoking this service. See
Table 11-122, "Virtual Processor Settings in Architectural Resources for
PAL_VPS_RESUME_NORMAL and PAL_VPS_RESUME_HANDLER" on page 2:489
details.
PAL_VPS_RESUME_NORMAL must be called with PSR.bn equal to 0.
If all virtualization accelerations and disables are disabled, PAL_VPS_RESUME_NORMAL
can also be used to resume to the guest independent on the state of vpsr.ic.
Table 11-122. Virtual Processor Settings in Architectural Resources for
Bank 1 GRs
FRs
Predicate Register
Branch Registers
Application Registers
Interval Timer Offset Register
Interruption Control Registers
Volume 2, Part 1: Processor Abstraction Layer
Description
VBR0
64-bit host virtual pointer to the Virtual Processor Descriptor (VPD)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PAL_VPS_RESUME_NORMAL and PAL_VPS_RESUME_HANDLER
Resource
Contains state of bank 0/1 GRs of the virtual processor (depends on
vpsr.bn.)
Contains floating-point register state of the virtual processor.
Contains the predicates of the virtual processor.
BR1-BR7 contains the state of the virtual processor. BR0 of the virtual
processor resides in bank 0 GR24.
Contains application register state of the virtual processor.
a
If guest MOV-from-AR.ITC optimization is enabled, this register contains
an offset, programmed by the VMM, to ensure that guest reads of ITC get
the proper value.
IIP, IPSR and IFS contains the IP, PSR and CFM of the virtual processor.
See Table 11-123
processor. The rest of the interruption control registers are don't cares. For
PAL_VPS_RESUME_HANDLER, the virtual interruption control registers
are specified in the VPD. See
on page 2:335
virtual processor.
PAL_VPS_RESUME_NORMAL
Description
for the PSR settings for the execution of the virtual
Section 11.7.4, "Virtualization Optimizations"
for synchronization of VPD resources before resuming the
for
2:489