Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 334

ld x = [b]
cmp.eq p1 = x, 'new'
(p1) br target
...
target:
ld y = [a]
if the second processor observes the store to [b], it will also observe the store to [a].
The flush cache (fc, fc.i) instruction follows data dependency ordering. fc and fc.i
are ordered only with respect to previous and subsequent load, store, or semaphore
instructions to the same line, regardless of the specified memory attribute. Subsequent
memory operations to the same line need not wait for prior fc or fc.i completion
before being globally visible. fc and fc.i are not ordered with respect to memory
operations to different lines. mf does not ensure visibility of fc and fc.i operations.
Instead, the sync.i instruction synchronizes fc and fc.i instructions, and the sync.i
is made visible using an mf instruction.
4.4.8 Not a Thing Attribute (NaTPage)
A NaTPage attribute prevents non-speculative references to a page, and ensures that
speculative references to the page always defer the Data NaT Page Consumption fault.
However, as described in
issue memory references to a NaTPage. As a result, all NaTPages must be backed by a
valid physical page.
Speculative or speculative advanced loads to pages marked as a NaTPage cause the
deferred exception indicator (NaT or NaTVal) to be written to the load target register,
and the memory reference is aborted. However, all other effects of the load instruction
such as post-increment are performed. Instruction fetches, loads, stores and
semaphores (including IA-32), but except for Itanium speculative loads, pages marked
as NaTPage raise a NaT Page Consumption fault.
A speculative reference to a page marked as NaTPage may still take lower priority
faults, if not explicitly deferred in the DCR.
page 2:105.
4.4.9 Effects of Memory Attributes on Memory Reference
Instructions
Memory attributes affect the following Itanium instructions.
• ldfe, stfe: Hardware support for 10-byte memory accesses to a page that is
neither a cacheable page with write-back write policy nor a NaTPage is optional. On
processor implementations that do not support such accesses, an Unsupported
Data Reference Fault is raised when an unsupported reference is attempted.
For extended floating-point loads the fault is delivered only on the normal,
advanced, and check load flavors (ldfe, ldfe.a, ldfe.c.nc, ldfe.c.clr). Control
speculative flavors of the ldfe instruction that target pages that are not cacheable
with write-back policy always defer the fault. Refer to
Faults" on page 2:105
• cmpxchg and xchg: These instructions are only supported to cacheable pages with
write-back write policy. cmpxchg and xchg accesses to NaTPages causes a Data NaT
2:86
"Speculation Attributes" on page
See "Deferral of Speculative Load Faults" on
for details.
2:79, the processor may
"Deferral of Speculative Load
Volume 2, Part 1: Addressing and Protection