Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 756

• Fence semantics combine acquire and release semantics (i.e. the instruction is
made visible after all prior orderable instructions and before all subsequent
orderable instructions).
In the above definitions "prior" and "subsequent" refer to the program-specified order.
An "orderable instruction" is an instruction that the memory ordering model can use to
establish ordering relationships
(from the standpoint of multiprocessor coherency) effects of performing an instruction.
Specifically,
• Accesses to uncacheable or write-coalescing memory regions are visible when they
reach the processor bus.
• Loads from cacheable memory regions are visible when they hit a
non-programmer-visible structure such as a cache or store buffer.
• Stores to cacheable memory regions are visible when they enter a snooped (in a
multiprocessor coherency sense) structure.
Memory access instructions typically have an ordered and an unordered form (i.e. a
form with unordered semantics and a form with either acquire, release, or fence
semantics). The Itanium architecture does not provide all possible combinations of
instructions and ordering semantics. For example, the Itanium instruction set does not
contain a store with fence semantics.
Section 4.4.7, "Memory Access Ordering" on page 1:73
"Sequentiality Attribute and Ordering" on page 2:82
instructions, and visibility in greater depth.
Section 2.2
memory ordering model.
2.1.2 Loads and Stores
In the Itanium architecture, a load instruction has either unordered or acquire
semantics while a store instruction has either unordered or release semantics. By using
acquire loads (ld.acq) and release stores (st.rel), the memory reference stream of
an Itanium architecture-based program can be made to operate according to the IA-32
ordering model. The Itanium architecture uses this behavior to provide IA-32
compatibility. That is, an Itanium acquire load is equivalent to an IA-32 load and an
Itanium release store is equivalent to an IA-32 store, from a memory ordering
perspective.
Loads can be either speculative or non-speculative. The speculative forms (ld.s,
ld.sa, and ld.a) support control and data speculation.
2.1.3 Semaphores
The Itanium architecture provides a set of three semaphore instructions: exchange
(xchg), compare and exchange (cmpxchg), and fetch and add (fetchadd). Both
cmpxchg and fetchadd may have either acquire or release semantics depending on the
1. The ordering semantics of an instruction do not imply the orderability of the instruction. Specifically,
unordered ordering semantics alone do not make an instruction unorderable; there are orderable
instructions with each of the four ordering semantics.
2:508
1
. The term "visible" refers to all architecturally-visible
on page 2:510 describes how the ordering semantics affect the Itanium
and Section 4.4.7,
discuss ordering, orderable
Volume 2, Part 2: MP Coherence and Synchronization