Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 397

1. Read and save the RSC, BSP and PFS application registers.
2. Issue a flushrs instruction to flush the dirty registers to the backing store.
3. Place RSE in enforced lazy mode by clearing both RSC.mode bits.
4. Read and save the RNAT application register.
5. Invalidate the ALAT using the invala instruction when switching from code that
does not restore RSE.BOF to its original setting. A different RSE.BOF will cause
program values in the new context to be placed in different physical registers.
See
6. Write the new context's BSPSTORE (was BSP after flushrs when switching out).
7. Write the new context's PFS and RNAT.
8. Write the new context's RSC which will set the RSE mode, privilege level and byte
order.
6.12 RSE Initialization
At processor reset the RSE is defined to be in enforced lazy mode, i.e., the RSC.mode
bits are both zero. The RSE privilege level (RSC.pl) is defined to be zero. RSE.BOF
points to physical register 32. The values of AR[PFS].pfm and CR[IFS].ifm are
undefined. The current frame marker (CFM) is set as follows: sof=96, sol=0, sor=0,
rrb.gr=0, rrb.fr=0, and rrb.pr=0. This gives the processor access to 96 stacked
registers.
The RSE performs no spill/fill operations until either an alloc, br.ret, rfi, flushrs or
loadrs require a mandatory RSE operation, or software explicitly enables eager RSE
operations. Software must provide the RSE with a valid backing store address in the
BSPSTORE application register prior to causing any RSE spill/fill operations. Failure to
initialize BSPSTORE results in undefined behavior.
Volume 2, Part 1: Register Stack Engine
"RSE and ALAT Interaction" on page 2:146 for details.
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