Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 672
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PAL_MC_ERROR_INJECT
Table 11-96. resources Return Value
Field
ibr0
ibr2
ibr4
ibr6
dbr0
dbr2
dbr4
dbr6
Multiprocessor coherency is not guaranteed when error injection is performed using this
procedure. Please refer to the processor-specific documentation for further details
regarding possible scenarios which can result in loss of coherency.
In cases where an error cannot be injected due to failure in locating the specified target
location (cache line, TC, TR, register number) for the given set of input arguments, the
procedure will return with status -4. For example, if the caller requests an error
injection in the cache and specifies cl_id=1 (virtual address provided), then PAL will
attempt to locate the cache line as indicated by the input virtual address. If the
corresponding cache line cannot be found (the cache line could have been evicted from
the cache in the time interval between the procedure call and the search process, or the
cache line may be in invalid state), then the procedure returns with a status value of -4.
The procedure does not check the settings of the error promotion bits (bit 53 and bit 60
in PAL_PROC_GET_FEATURES) before injecting an error in the specified structure.
Based on the configuration of these bits, the severity of the error reported may vary.
The detailed descriptions of err_struct_info and err_data_buffer are shown below.
Figure 11-27. err_struct_info – Cache
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
Table 11-97. err_struct_info – Cache
Field
siv
c_t
cl_p
2:424
Bits
0
When 1, indicates that IBR0,1 are being used by the procedure for trigger functionality.
1
When 1, indicates that IBR2,3 are being used by the procedure for trigger functionality.
2
When 1, indicates that IBR4,5 are being used by the procedure for trigger functionality.
3
When 1, indicates that IBR6,7 are being used by the procedure for trigger functionality.
4
When 1, indicates that DBR0,1 are being used by the procedure for trigger functionality.
5
When 1, indicates that DBR2,3 are being used by the procedure for trigger functionality.
6
When 1, indicates that DBR4,5 are being used by the procedure for trigger functionality.
7
When 1, indicates that DBR6,7 are being used by the procedure for trigger functionality.
Reserved
Reserved
Bits
0
When 1, indicates that the structure information fields (c_t,cl_p,cl_id) are valid and
should be used for error injection. When 0, the structure information fields are ignored,
and the values of these fields used for error injection are implementation-specific.
2:1
Indicates which cache should be used for error injection:
0 – Reserved
1 – Instruction cache
2 – Data or unified cache
3 – Reserved
5:3
Indicates the portion of the cache line where the error should be injected:
0 – Reserved
1 – Tag
2 – Data
3 – mesi
All other values are reserved.
Description
9
8
7
6
cl_dp
cl_id
41
40 39
38
trigger_pl
Description
Volume 2, Part 1: Processor Abstraction Layer
5
4
3
2
1
0
cl_p
c_t siv
37 36 35 34 33 32
trigger
tiv
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