Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 841

Just as for overflow, the actual scaling of the result is not performed by the Itanium
architecture. It is typically performed by the IEEE Filter, which is invoked before calling
the user floating-point exception handler.
8.1.2.6 Inexact Exception (Trap)
The exception-enabled response of an Itanium arithmetic instruction to an Inexact
exception is to set the I bit (and possibly the FPA bit) in the ISR.code field of the ISR
register and the Inexact flag in the appropriate status field of the FPSR register. The
operating system kernel, reached via the floating-point fault vector, will then invoke the
user floating-point exception handler, if one has been registered.
8.2 IA-32 Floating-point Exceptions
IA-32 floating-point exceptions may occur when executing code in IA-32 mode. When
this happens, execution is transferred to the Itanium interruption vector for IA-32
Exceptions (at vector address 0x6900.) For classic IA-32 floating-point instructions,
they are raised via the "IA_32_Exception(FPError)
SSE instructions, they are raised via the "IA_32_Exception(StreamingSIMD)
Numeric Error Fault." The operating system may schedule Itanium architecture-based
and/or IA-32 exception handlers for these exceptions.
Volume 2, Part 2: Floating-point System Software
Pending Floating-point Error." For
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