Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 303

Table 4-3.
TLB
Field
p GR[r]{0}
ma GR[r]{4:2}
a GR[r]{5}
d GR[r]{6}
pl GR[r]{8:7}
ar GR[r]{11:9}
ppn GR[r]{49:12}
ig GR[r]{63:53}
IFA{11:0},
RR[vrn]{0,7:2}
ed GR[r]{52}
ps ITIR{7:2}
key ITIR{31:8}
vpn IFA{63:12}
rid RR[VRN].rid
The format in
Volume 2, Part 1: Addressing and Protection
Translation Interface Fields (Continued)
Source
Field
Present bit – When 0, references using this translation cause an Instruction or
Data Page Not Present fault. Most other fields are ignored by the processor,
see Figure 4-6
mapped physical page is not resident in physical memory. The present bit
is not a valid bit. For each TLB entry, the processor maintains an
additional hidden valid bit indicating if the entry is enabled for matching.
Memory Attribute – describes the cacheability, coherency, write-policy and
speculative attributes of the mapped physical page. See
on page 2:75
Accessed Bit – When 0 and PSR.da is 0, data references to the page cause a
Data Access Bit fault. When 0 and PSR.ia is 0, instruction references to the
page cause an Instruction Access Bit fault. When 0, IA-32 references to the
page cause an Instruction or Data Access Bit fault. This bit can trigger a fault
on reference for tracing or debugging purposes. The processor does not
update the Accessed bit on a reference.
Dirty Bit – When 0 and PSR.da is 0, Intel Itanium store or semaphore
references to the page cause a Data Dirty Bit fault. When 0, IA-32 store or
semaphore references to the page cause a Data Dirty Bit fault. The processor
does not update the Dirty bit on a store or semaphore reference.
Privilege Level – Specifies the privilege level or promotion level of the page.
See "Page Access Rights" on page 2:56
Access Rights – page granular read, write and execute permissions and
privilege controls. See
Physical Page Number – Most significant bits of the mapped physical address.
Depending on the page size used in the mapping, some of the least significant
PPN bits are ignored.
available – Software can use these fields for operating system defined
parameters. These bits are ignored when inserted into the TLB by the
processor.
Exception Deferral – For a speculative load that results in an exception, the
speculative load's instruction page TLB.ed bit is one of the conditions which
determines whether the exception must be deferred. See
Speculative Load Faults" on page 2:105
ignored in the data TLB for data memory references and for IA-32 memory
references.
Page Size – Page size of the mapping. For page sizes larger than 4K bytes
the low-order bits of PPN and VPN are ignored. Page sizes are defined as 2
bytes. See "Page Sizes" on page 2:57
Protection Key – Uniquely tags the translation to a protection domain. If a
translation's Key is not found in the Protection Key Registers (PKRs), access
is denied and a Data or Instruction Key Miss fault is raised. See
Keys" on page 2:59
checked on a TLB insert instruction, ITIR{31:8} may be ignored if GR[r]{0} is
zero (not-present Translation Insertion Format).
Virtual Page Number – Depending on a translation's page size, some of the
least-significant VPN bits specified are ignored in the translation process.
VPN{63:61} (VRN) selects the region register.
Virtual Region Identifier – On TLB inserts the Region Identifier selected by
VPN{63:61} (VRN) is used as additional match bits for subsequent accesses
and purges (much like vpn bits).
Figure 4-6 is defined for not-present translations (P-bit is zero).
Description
for details. This bit is typically used to indicate that the
for details.
for complete details.
"Page Access Rights" on page 2:56
for complete details. This bit is
for a list of supported page sizes.
for complete details. In implementations where ITIR is
"Memory Attributes"
for details.
"Deferral of
ps
"Protection
2:55