11.1.3
PAL Entrypoints
The following hardware events can trigger the execution of a PAL entrypoint:
• Power-on/reset
• Hardware errors (both correctable and uncorrectable)
• Initialization event (via external interrupt bus message or processor pin)
• Platform management interrupt (via external interrupt bus message or processor
pin)
These hardware events trigger the execution of one of the following PAL entrypoints (as
shown in
• PALE_RESET
then branches to SALE_ENTRY to determine whether to perform firmware recovery
update, or to boot the machine for OS use. See
on page
• PALE_CHECK
error information and corrects errors where possible (for example, by flushing a
corrupted instruction cache line and marking the cache line as unusable). In all
cases, PALE_CHECK branches to SALE_ENTRY to complete the error logging,
correction, and reporting.
• PALE_INIT
branches to SALE_ENTRY. PALE_INIT is entered as a response to an initialization
event.
• PALE_PMI
entered as a response to a platform management interrupt.
11.1.4
SAL Entrypoints
There are two entrypoints from PAL into SAL:
• SALE_ENTRY
machine check, or initialization event. If SALE_ENTRY was invoked by a machine
check or initialization event, SALE_ENTRY branches to the appropriate routine:
• SAL_CHECK is invoked after a machine check.
• SAL_INIT is invoked after an initialization event.
If SALE_ENTRY was invoked by a reset or power on, it checks to determine if a
firmware recovery condition exists. If it does, SALE_ENTRY performs the firmware
update, then performs a RESET operation to invoke PAL_RESET. If a recovery
condition does not exist, SAL_ENTRY returns to PAL_RESET to complete processor
self-test. PAL_RESET then branches back to SALE_ENTRY, which, in turn, branches
to SAL_RESET.
• SALE_PMI
entrypoint after saving processor state in response to the platform management
interrupt.
2:282
Figure
11-2):
Initializes and tests the processor following power-on or reset and
–
2:282.
Determines if errors are processor related, saves processor related
–
Saves the processor state, places the processor in a known state, and
–
Saves the processor state and branches to SALE_PMI. PALE_PMI is
–
PAL branches to this SAL entrypoint after a power-on, reset,
–
platform management interrupt. PALE_PMI branches to this SAL
–
Section 11.1.4, "SAL Entrypoints"
Volume 2, Part 1: Processor Abstraction Layer
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