Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 517

Figure 10-2.
IA-32
IN,
OUT
®
Intel
Itanium
Load,
Store
For IA-32 IN and OUT instructions a port's virtual address is computed as:
port_virtual_address = IOBase | (port{15:2}<<12) | port{11:0}
This address computation places 4 ports on each 4K page and expands the space to
64MB, with the ports being at a relative offset specified by port{11:0} within each
4K-byte virtual page. IOBase is a kernel register (KR) maintained by the operating
system that points to the base of the 64MB Virtual I/O port space. The value in IOBase
must be aligned on a 64MB boundary otherwise port address aliasing will occur and
processor operation is undefined.
For Itanium load and stores accesses to the I/O port space, a port's virtual address can
be computed in the same manner, specifically.
port_virtual_address = IOBase | (port{15:2}<<12) | port{11:0}
In practice this address is a constant for any given physical I/O device.
Note: In the generation of the I/O port virtual address, software MUST ensure that
port_virtual_address{11:2} are equal to port{11:2} bits. Otherwise, some pro-
cessors implementations may place the port data on the wrong bytes of the
processor's bus and the port will not be correctly accessed.
IA-32 IN and OUT instructions and Itanium or IA-32 load/store instructions can
reference I/O ports in 1, 2, or 4-byte transactions. References to the legacy I/O port
space cannot be performed with greater than 4 byte transactions due to bus limitations
in most systems. Since an IA-32 IN/OUT instruction can access up to 4 bytes at port
address 0xFFFF, the I/O port space effectively extends 3 bytes beyond the 64KB
boundary. Operating systems can; 1) not map the excess 3 bytes, resulting in denial of
permission for the excess 3 bytes, or 2) map via the TLB the excess 3 bytes back to
port address 0 effectively wrapping the I/O port space at 64KB.
Operating system code can map each virtual I/O port space page anywhere within the
physical address space using the Data Translation Registers or the Data Translation
Cache. Large page translations can be used to reduce the number of mappings required
in the TLB to map the I/O port space. For example, one 64MB translation is sufficient to
map the entire expanded 64MB I/O port space. The UC memory attribute must be
used for all I/O port space mappings to avoid speculative processor references to I/O
devices, otherwise processor and platform operation is undefined.
®
Volume 2, Part 1: Itanium Architecture-based Operating System Interaction Model with IA-32 Applications
I/O Port Space Addressing
Port{15:2}
I/O Port
Number
Port{11:0}
®
I/O Port
Address
64-bit Virtual
IOBase
Address
Shift
Left
OR
12-bits
64-bit
Physical Address
TLB
2:269