Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 506

Table 10-5.
IA-32 Instruction
MOV from CR
MOV to CR
MOV to/from DR
Mov SS
MOVAPS, MOVHPS,
MOVLPS. MOVMSKPS,
MOVSS, MOVUPS
MOVD, MOVQ
MOVS
MOVSX, MOVZX
MUL
MULPS, MULSS
NEG
NOP
NOT
OR
ORPS
OUT, OUTS
PACKSS, PACKUS
PADD, PADDS, PADDUS
PAND, PANDN
PCMPEQ, PCMPGT
PEXTRW, PINSRW
PMADD
PMULHW, PMULLW,
PMULHUW
PMOVMSKB
POP, POPA
POP SS
POPF, POPFD
POR
PREFETCH
PSHUFW
PSLL, PSRA, PSRL
PSUB, PSUBS, PSUBUS
PUNPCKH, PUNPCKL
PXOR
PUSH, PUSA
PUSHF, PUSHFD
RCL, RCR, ROL, ROR
RCPPS, RSQRTPS
RDMSR
RDTSC
RDPMC
REP, REPcc prefix
2:258 Volume 2, Part 1: Itanium
IA-32 Instruction Summary (Continued)
® ®
Intel Itanium System
Environment
unchanged
Instruction Intercept
System Flag Intercept Trap
unchanged
unchanged + I/O ports are
mapped virtually
unchanged
System Flag Intercept
Optional System Flag
Intercept
unchanged
unchanged
Instruction Intercept
Optional GPFault
unchanged
®
Architecture-based Operating System Interaction Model with IA-32 Applications
Comments
IA-32 privileged system registers
System Flag Intercept Trap after instruction
completes
If CFLG.io is 0, the TSS I/O permission bitmap is
not consulted. Intel Itanium TLB faults control
accessibility to I/O ports.
System Flag Intercept Trap after instruction
completes
Intercept if EFLAG.if changes state and CFLG.ii is 1
Intercept if EFLAG.ac, or tf change state.
Pushes value in EFLAG, no intercept
IA-32 privileged system register space
No longer faults in VM86, GPFault if secured by
PSR.si or CFLG.tsd.