Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 663

Table 11-90. cache_check Fields (Continued)
Field
rsvd
hlth
index
rsvd
is
iv
pl
pv
mcc
tv
rq
rp
pi
a. Hardware is tracking the operating status of the structure type and level reporting the error. The hardware
reports a "normal" status when the number of entries within a structure reporting repeated corrections is at or
below a pre-defined threshold. A "cautionary" status is reported when the number of affected entries exceeds
a pre-defined threshold.
TLB_Check Return Format: The tlb_check return format is returned in error_info
when the user requests information on any instruction or data/unified TLB in the
level_index input argument. The tlb_check return format is a bit-field that is described
in Figure 11-21
Figure 11-21. tlb_check Layout
31 30 29 28
hlth
63 62 61 60
pi rp rq tv mcc pv
Table 11-91. tlb_check Fields
Field
tr_slot
trv
Volume 2, Part 1: Processor Abstraction Layer
Bits
29:24 Reserved
31:30 Health indicator. This field will report if the cache type and level reporting this error
supports hardware status tracking and the current status of this cache.
00 – No hardware status tracking is provided for the cache type and level reporting this
event.
01 – Status tracking is provided for this cache type and level and the current status is
a
normal status.
10 – Status tracking is provided for the cache type and level and the current status is
a
cautionary. When a cache reports a cautionary status the "hardware damage" bit of the
PSP (see Figure 11-11, "Processor State Parameter," on page
11 – Reserved
51:32 Index of the cache line where the error occurred.
53:52 Reserved
54 Instruction set. If this value is set to zero, the instruction that generated the machine
check was an Intel Itanium instruction. If this bit is set to one, the instruction that
generated the machine check was IA-32 instruction.
55 The is field in the cache_check parameter is valid.
57:56 Privilege level. The privilege level of the instruction bundle responsible for generating the
machine check.
58 The pl field of the cache_check parameter is valid.
59 Machine check corrected: This bit is set to one to indicate that the machine check has
been corrected.
60 Target address is valid: This bit is set to one to indicate that a valid target address has
been logged.
61 Requester identifier: This bit is set to one to indicate that a valid requester identifier has
been logged.
62 Responder identifier: This bit is set to one to indicate that a valid responder identifier has
been logged.
63 Precise instruction pointer. This bit is set to one to indicate that a valid precise instruction
pointer has been logged.
and Table 11-91.
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reserved op itc dtc itr dtr
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
pl iv is
Bits
7:0 Slot number of the translation register where the failure occurred.
8 The tr_slot field in the TLB_check parameter is valid.
PAL_MC_ERROR_INFO
Description
2:299) will be set as well.
8 7
reserved level rv trv
reserved
Description
6 5 4 3 2 1 0
tr_slot
2:415