Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 412

When switching back to the original context (that originally caused the counter
overflow), the previously saved freeze bit can be inspected. If it was set (meaning there
was a pending performance monitor interrupt), then the context switch routine posts
an interrupt message to the incoming context's processor at the performance monitor
vector specified by the PMV register (see
Layout and Example" on page
overflow interrupt in the correct context. Essentially, the interrupt message is
"replaying" the overflow interrupt that was missed because of the context switch.
Figure 7-8.
// in context or thread switch
if (outgoing process is monitored) {
1. Turn-off counting and ignore interrupts for context switch
of counters.
1a)
1b)
1c)
1d)
2. Preserve PMC/PMD contents
2a)
2b) For each PMD whose PALPMDmask bit is set, preserve PMD.
}
.... continue context switch ......
// Now in incoming process/thread
if (incoming process is monitored) {
// Event counting is disabled because PSR.up and pp are both
// zero (step 1c above).
3. Restore PMC/PMD contents (inverse of step 4 above)
3a) For each PMC whose PALPMCmask bit is set, reload PMC.
3b) For each PMD whose PALPMDmask bit is set, reload PMD.
4. Restore Interrupt State (inverse of step 2 and 1a above)
4a)
4b)
4c)
4d)
}
2:164
2:612). This will result in a new performance monitor
Performance Monitor Overflow Context Switch Routine
if not already done, raise interrupt priority above
perf. mon overflow vector
read and preserve PSR.up, PSR.pp, PSR.sp
clear PSR.up, clear PSR.pp
srlz.d
For each PMC whose PALPMCmask bit is set, preserve PMC.
if (PMC[0].fr) {
send myself a performance monitor interrupt
(store to interrupt address)
}
Restore PSR.up and PSR.pp
srlz.d
lower interrupt priority below perf. mon overflow
vector
Section 10.5.8, "Inter-processor Interrupts
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Volume 2, Part 1: Debugging and Performance Monitoring