Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 276

Table 3-2.
Field
ss 40
ri 42:41
ed 43
bn 44
ia 45
vm 46
rv 63:47
2:28
Processor Status Register Fields (Continued)
Bits
Single Step enable – When 1, a Single Step trap occurs
following the successful execution of the first restart
instruction in the current bundle. Instruction slots 0, 1,
and 2 can be single stepped. When 1 or EFLAG.tf is 1,
an IA_32_Exception(Debug) trap is taken after each
IA-32 instruction.
Restart Instruction – Set on an interruption, indicating
the next instruction in the bundle to be executed. When
the next instruction is the L+X instruction of an MLX,
this field is set to the value 1.
When restarting instructions with rfi, this field in IPSR
specifies which instruction(s) in the bundle are
restarted. The specified and subsequent instructions
are restarted, all instructions prior to the restart point
are ignored.
0 – restart execution at instruction slot 0
1 – restart execution at instruction slot 1
2 – restart execution at instruction slot 2
3 – reserved
Except at an interruption and for the first restart
instruction following an rfi, the value of this field is
undefined.
This field is set to 0 after any interruption from the IA-32
instruction set and is ignored when IA-32 instructions
are restarted.
Exception Deferral – When 1, if the first restart
instruction in the current bundle is a speculative load,
the operation is forced to indicate a deferred exception
by setting the load target register to NaT or NaTVal. No
memory references are performed, however any
address post increments are performed. If the operation
is a speculative advanced load, the ALAT entry
corresponding to the load address and target register is
purged. If the operation is an lfetch instruction,
memory promotion is not performed, however any
address post increments are performed. When 0,
exception deferral is not forced on restarted speculative
loads. If the first restart instruction is not a speculative
load or lfetch instruction, this bit is ignored.
register Bank – When 1, registers GR16 to GR31 for
bank 1 are accessible. When 0, registers GR16 to
GR31 for bank 0 are accessible. Written by rfi and
bsw instructions.
Disable Instruction Access-bit faults – When 1,
Instruction Access-Bit faults are disabled on the first
restart instruction in the current bundle.
Access-bit faults are not affected by PSR.ia.
Virtual Machine – When 1, an attempt to execute
certain instructions results in a Virtualization fault.
Implementation of this bit is optional. If the bit is not
implemented, it is treated as a reserved bit. Written by
the rfi and vmsw instructions.
reserved
Description
kl
k
IA-32
l
Volume 2, Part 1: System State and Programming Model
Interruption Serialization
State Required
g
0 rfi
g
instruction rfi
pointer
g
0 rfi
m
0 implicit
g
0 rfi
0 rfi,
vmsw: implicit
n