Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 592

corresponding NaT bits from the VPD. vpsr.bn is updated to reflect the new register
bank without any intercepts to the VMM, unless a fault condition is detected (see
Table 11-46
If this optimization is disabled, execution of the bsw instruction with PSR.vm==1
results in a virtualization intercept.
Synchronization is required when this optimization is enabled, see
details.
Table 11-40. Synchronization Requirements for Bank Switch Optimization
vpsr.bn
Table 11-41. Interruptions when Bank Switch Optimization is Enabled
bsw
Note: This field cannot be enabled together with the d_psr_i virtualization disable
control (vdc) described in
alization" on page
control, an error will be returned during PAL_VP_CREATE and
PAL_VP_REGISTER. See
nations" on page 2:349
11.7.4.2.8 Probe Instruction Virtualization
The probe instruction virtualization is controlled by the a_all_probes and
a_select_probes bits in the Virtualization Acceleration Control (vac) field in the VPD.
When the a_all_probes bit is set to 1, all probe instructions running at all privilege
levels with PSR.vm==1 will result in virtualization intercepts.
When the a_select_probes bit is set to 1, the following probe instructions will raise
virtualization intercepts when executed with PSR.vm==1 at the most privileged level
(VPSR.cpl==0):
• probe instructions in immediate-form, with immediate field equal to privilege level
0
• All probe instructions in register-form
Please refer to the instruction description page for the probe instruction for details on
the usage of immediate-form and register-form of the instruction.
Note: Software cannot enable both a_all_probes and a_select_probes bits together -
an error will be returned during PAL_VP_CREATE and PAL_VP_REGISTER.
The virtualization of
implementations. Software can call PAL_VP_ENV_INFO to determine the availability of
this feature.
2:344
for details).
VPD Resource
Instructions
2:348. If this control is enabled together with the d_psr_i
for details.
instructions is not supported on all processor
probe
Synchronization Required
Read, Write
Interruptions
When the bank switch optimization is enabled, bsw instructions with
PSR.vm==1, may raise the following faults:
• Illegal Operation fault – if the instruction is not the last instruction
in an instruction group
• Privileged Operation fault – if vpsr.cpl is not zero
Section 11.7.4.3.7, "Disable PSR Interrupt-bit Virtu-
Section 11.7.4.4, "Virtualization Optimization Combi-
Volume 2, Part 1: Processor Abstraction Layer
Table 11-40 for