Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 328

Prefetches are enabled if a speculative translation exists. Prefetches are asynchronous
data and instruction memory accesses that appear logically to initiate and finish
between some pair of instructions. This access may not be visible to subsequent flush
cache (fc, fc.i) and/or TLB purge instructions. This behavior is
implementation-dependent.
The processor will not initiate memory references (16-byte instruction bundle fetches,
IA-32 instruction fetches, RSE fills and spills, VHPT references, and data memory
accesses) to non-speculative pages until all previous control dependencies (predicates,
branches, and exceptions) are resolved; i.e., the memory reference is required by an
in-order execution of the program. Additionally, for references to non-speculative
pages, the processor:
• May not generate any memory access for a control or data speculative data
reference.
• Will generate exactly one memory access for each aligned, non-speculative data
reference. (Misaligned data references may cause multiple memory accesses,
although these accesses are guaranteed to be non-overlapping – each byte will be
accessed exactly once.)
• May generate multiple 16-byte memory accesses (to the same address) for each
16-byte instruction bundle fetch reference.
To ensure virtual and physical accesses to non-speculative pages are performed in
program order and only once per program order occurrence, the rules in
Table 4-14
not performed to non-speculative memory that may contain I/O devices; otherwise,
system behavior is undefined.
Table 4-13.
Memory
Attribute
Speculative
Non-speculative
Limited Speculation
a. Includes the faulting form of line prefetch (lfetch.fault).
b. Includes the non-faulting form of line prefetch (lfetch), which does not cause a cache fill if the memory
attribute is non-speculative or limited speculation.
c. Hardware-generated speculative references include non-demand instruction prefetches (including IA-32),
hardware-generated data prefetch references, and eager RSE memory references.
d. The processor may only issue hardware-generated speculative references to a 4K-byte physical page if it is a
verified page.
Table 4-14.
Memory
Attribute
Speculative
Non-speculative
Limited Speculation
2:80
are defined. Software should also ensure that RSE spill/fill transactions are
Permitted Speculation
Speculative
Load
Load
a
(ld)
(ld.s)
Yes Yes
Yes Always Fail
Yes Always Fail
Register Return Values on Non-faulting Advanced/Speculative
Loads
Speculative Load
(ld.s)
Success Failure
Value Nat
N/A Nat
N/A Nat
Advanced Speculative
Load Advanced
b
(ld.a) Load (ld.sa)
Yes Yes
Always Fail Always Fail
Yes Always Fail
Advanced Load
(ld.a)
Success Failure
a
Value N/a
b c
N/A Zero
b
Value N/a
Volume 2, Part 1: Addressing and Protection
Table 4-13
Hardware-generated
Speculative
References
Yes
Prohibited
d
Limited
Speculative Advanced Load
(ld.sa)
Success Failure
a
Value NaT
b
N/A NaT
b
N/a NaT
and
c