Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 366

Figure 5-5.
CPU Receives
Interrupt n
pending[n] = 1
in-service[n] = 0
OS Completes Interrupt
n (Writes to EOI)
5.8.1 Interrupt Vectors and Priorities
As indicated in
turn have higher priority than external interrupts. PMIs and external interrupts are
further prioritized by vector number.
PMIs have a separate vector space from external interrupts. PMI vectors 0-3 can be
used by platform firmware. PMI vectors 4 through 15 are reserved for use by processor
firmware. Assertion of the processor's PMI pin, when present, results in PMI vector
number 0. PMI vector priorities are described in
Interrupt (PMI)" on page
Each external interrupt (INT) in the system is distinguished from other external
interrupts by a unique vector number. There are 256 distinct vector numbers in the
range 0 - 255. Vector numbers 1 and 3 through 14 are reserved for future use. Vector
number 0 (ExtINT) is used to service Intel 8259A-compatible external interrupt
controllers. Vector number 2 is used for the Non-Maskable Interrupt (NMI). The
remaining 240 external interrupt vector numbers (16 through 255) are available for
general operating system use.
2:118
External Interrupt States
pending[n] = 0
in-service[n] = 0
Level-sensitive Interrupt
Signal n is Deasserted
PENDING
OS Acquires Interrupt n
(Reads IVR)
pending[n] = 1
in-service[n] = 1
Table 5-6 on page 2:109, INITs have higher priority than PMIs, which in
2:310.
Table 5-8
INACTIVE
Level-sensitive Interrupt
Signal n is Deasserted
IN-SERVICE
One Pending
Section 11.5, "Platform Management
summarizes the interrupt priority model.
OS Completes Interrupt
n (writes to EOI)
IN-SERVICE
None Pending
pending[n] = 0
in-service[n] = 1
CPU Receives
Interrupt n
Volume 2, Part 1: Interruptions