Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 452
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Floating-point Trap vector (0x5d00)
Name
Cause
A floating-point exception trap has occurred. IA-32 numeric instructions can not raise
this trap.
Interruptions on this vector:
Floating-Point Exception trap
Parameters
IIP, IPSR, IIPA, IFS – are defined; refer to
IIB0, IIB1 – If implemented, the IIB registers contain the instruction bundle pointed to
by IIPA. Please refer to
(IIB0-1 – CR26, 27)" on page 2:42
ISR – The ISR.ei bits are set to indicate which instruction caused the exception.
ISR.code contains information about the type of FP exception and IEEE information.
The ISR code field contains a bit vector (see
which occurred in the just-executed instruction. The defined ISR bits are specified
below:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
2:204
Section 3.3.5.10, "Interruption Instruction Bundle Registers
0
0
0
page 2:165
for a detailed description.
for details on the IIB registers.
Table 8-3 on page
0
fp trap code
0
Volume 2, Part 1: Interruption Vector Descriptions
2:170) for all traps
8
7
6
5
4
3
2
0 0 0 ss 0 0 1
ei
0 ni 0 0 0 0 0 0 0
1
0
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