Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 595

Table 11-46. Virtualization Disables Summary (Continued)
Disable ITM Virtualization
Disable PSR Interrupt-bit Virtualization
a. The Virtualization Disable Control (vdc) field resides in the Virtual Processor Descriptor (VPD), see
Section 11.7.1, "Virtual Processor Descriptor (VPD)" on page 2:325
11.7.4.3.1 Disable VMSW Instruction
The VMSW instruction disable is controlled by the d_vmsw bit in the Virtualization
Disable Control (vdc) field in the VPD. When this control is set to 1, the vmsw instruction
is disabled on the logical processor. Execution of the vmsw instruction, independent of
the state of PSR.vm, results in a virtualization intercept.
If this control is set to 0, the vmsw instruction can be executed by both the VMM and
guest without virtualization intercepts, if PSR.it is 1 and the vmsw instruction is
executed on a page with access rights of 7.
11.7.4.3.2 Disable External Interrupt Control Register Virtualization
The external interrupt control register virtualization disable is controlled by the d_extint
bit in the Virtualization Disable Control (vdc) field in the VPD. When this control is set to
1, the external interrupt control registers (CR65-71) are not virtualized, and code
running with PSR.vm==1 can read and write these resources directly without any
intercepts to the VMM.
If this control is set to 0, accesses (reads/writes) to the external interruption control
registers with PSR.vm==1 result in virtualization intercepts.
Note: This field cannot be enabled together with the a_int virtualization acceleration
control (vac) described in
mization" on page
trol, an error will be returned during PAL_VP_CREATE and PAL_VP_REGISTER.
See
page 2:349
11.7.4.3.3 Disable Breakpoint Register Virtualization
The breakpoint register virtualization disable is controlled by the d_ibr_dbr bit in the
Virtualization Disable Control (vdc) field in the VPD. When this control is set to 1,
accesses (reads/writes) to the data and instruction breakpoint registers (DBR/IBR) are
not virtualized, and code running with PSR.vm==1 can read and write these resources
directly without any intercepts to the VMM.
If this control is set to 0, accesses (reads/writes) to the breakpoint registers with
PSR.vm==1 result in virtualization intercepts.
Volume 2, Part 1: Processor Abstraction Layer
Disable
Section 11.7.4.2.1, "Virtual External Interrupt Opti-
2:338. If this control is enabled together with the a_int con-
Section 11.7.4.4, "Virtualization Optimization Combinations" on
for details.
Virtualization
Disable Control Description
a
(vdc)
d_itm Section 11.7.4.3.6
d_psr_i Section 11.7.4.3.7
for details.
2:347