Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 500

10.3.3.3 IA-32 Memory Type Range Registers (MTRRs)
Within the Itanium System Environment, IA-32 MTRR registers are superseded by
physical memory attributes supplied by the TLB, as defined in
"Cacheability and Coherency Attribute" on page
the MTRRs in the MSR register space results in an instruction intercept fault.
10.3.3.4 IA-32 Model Specific and Test Registers
Within the Itanium System Environment, the IA-32 Model Specific Register space
(MSRs) are superseded by the PAL firmware interface. Cache testing, initialization,
processor configuration should be performed through the PAL interface. See
Section 11.10, "PAL Procedures" on page 2:353
functions and interfaces. Accesses to the IA-32 Model Specific Register space result in
an instruction interception fault.
10.3.3.5 IA-32 Performance Monitor Registers
Within the Itanium System Environment, the Itanium performance monitors are
designed to measure IA-32 and Itanium instructions, and system performance through
a unified performance monitoring facility. Itanium architecture-based code can program
the performance monitors for IA-32 and/or Itanium events by configuring the PMC
registers. Count values are accumulated in the PMD registers for both IA-32 and
Itanium events. See implementation-specific documentation for the list of supported
events and encodings.
IA-32 code can sample the performance counters by issuing the RDPMC instruction.
RDPMC returns count values from the specified Itanium performance monitor.
Operating systems can secure the monitors from being read by IA-32 code by setting
PSR.sp to 1, or setting CR4.pce to 0, or setting the performance monitor's pm-bit.
Reads of a secured counter by RDPMC return a IA_32_Exception(GPFault(0)). IA-32
code cannot write or configure the performance monitors, all writes to the MSR register
space are intercepted.
10.3.3.6 IA-32 Machine Check Registers
Within the Itanium System Environment, IA-32 machine check registers are
superseded by the Itanium machine check architecture. See
Checks" on page 2:296
check registers results in an instruction intercept.
10.4 Register Context Switch Guidelines for IA-32 Code
The following section gives operating system performance guidelines to minimize the
amount of register context that must be saved and restored for IA-32 processes during
a context switch.
2:252 Volume 2, Part 1: Itanium
for details. IA-32 accesses to the Pentium III Processor machine
®
Architecture-based Operating System Interaction Model with IA-32 Applications
Section 4.4.3,
2:77. IA-32 instruction references to
for a complete definition of the PAL
Section 11.3, "Machine