Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 650
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PAL_HALT_INFO
The latency numbers given are the minimum number of processor cycles that will be
required to transition the states. The maximum or average cannot be determined by
PAL due to its dependency on outstanding bus transactions.
For more information on power management, please refer to Section 11.6, "Power
Management" on
2:402
page
2:313.
Volume 2, Part 1: Processor Abstraction Layer
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