Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 340

3. Execute:
mf ;;
srlz.i ;;
(The ensures visibility of ptr.d, ptr.i, or ptc.ga to both data and instruction
stream, so that no new prefetches will be done to the old translations.)
4. Call PAL_PREFETCH_VISIBILITY with the input argument trans_type equal to one
to indicate that the transition is for all memory attributes. This PAL call
terminates the processor's rights to make speculative references to any limited
speculation pages (i.e., it causes all WBL pages to no longer be verified pages –
see the discussion on limited speculation in
and the WBL Physical Addressing Attribute" on page
prefetches in flight have been completed. The return argument from this
procedure informs the caller if this procedure call is needed on remote processors
or not. If this procedure call is not needed on remote processors, and step 2.b
was used above, then software may skip the IPI in step 5 and go straight to step
6 below.
5. If step 2.a was performed, or if the PAL_PREFETCH_VISIBILITY return argument
indicated the call must be made on other processors in the coherency domain,
then use the IPI mechanism defined in
Interrupt Messages" on page 2:128
domain. If step 2a was performed, then steps 2 through 4 must be performed on
all processors in the coherency domain. Otherwise, only step 4 must be
performed. Wait for all PAL_PREFETCH_VISIBILITY calls to complete on all
processors in the coherency domain before continuing. After step 5, no more new
instruction or data prefetches will be made to page ''X'' by any processor in the
coherency domain. However, processor caches in the coherency domain may still
contain ''stale'' data or instructions from prior prefetch or memory references to
page ''X.''
6. Perform one of the following steps:
a. Call PAL_CACHE_FLUSH with input parameters cache_type=3 and
b. On the processor where the OLD was initiated, perform the sequence:
Note: If the memory range being OLDed is much larger than the caches being
7. Call PAL_MC_DRAIN.
2:92
operation.inv=1, or
i. If the sequence is to be executed with PSR.dt=1, then insert a temporary
translation for the memory range with the ''UC'' memory attribute.
ii. Execute the following instruction sequence:
fc [X] // flush all processor caches in the coherence domain
fc [X+32]
fc [X+64]
... // ... for the memory range being OLDed
fc [X+ps-32] ;;
// Ensure cache flushes are also seen
// by processors' instruction fetch
sync.i ;;
iii. If the sequence had been run with PSR.dt=1, then remove the temporary
translation inserted in step 6.b.i.
flushed, option 6.a. may be significantly faster.
Section 4.4.6.1, "Limited Speculation
2:81.). It also ensure all
Section 5.8.4.1, "Inter-processor
to reach all processors in the coherency
Volume 2, Part 1: Addressing and Protection