Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 441

• ISR.code{7:4} = 1: Privileged Operation fault. Cannot be raised by IA-32
instructions.
• ISR.code{7:4} = 2: Privileged Register fault. Cannot be raised by IA-32
instructions.
• ISR.code{7:4} = 3: Reserved Register/Field fault, Unimplemented Data Address
fault or IR Unimplemented Data Address fault. Cannot be raised by IA-32
instructions. For Unimplemented Data Address fault:
• If ISR.rs = 0: A data memory reference to an unimplemented address has
occurred.
• If ISR.rs = 1: A mandatory RSE reference to an unimplemented address has
occurred.
For details, refer to
"Unimplemented Address Bits" on page
Volume 2, Part 1: Interruption Vector Descriptions
• If the instruction has two PR targets, and specifies the same PR for both,
predicated-off unconditional compare, fclass, tbit, tnat, and tf
instructions take this fault, even when their qualifying predicate is zero.
• Register bank conflict on a floating-point load pair instruction.
• An access to BSPSTORE or RNAT is performed with a non-zero RSC.mode,
or a loadrs is performed with a non-zero RSC.mode.
• A loadrs is performed with a non-zero CFM.sof and a non-zero RSC.loadrs,
or a loadrs causes more registers to be loaded from memory than can fit
in the physical stacked register file.
• Attempts to predicate a br.ia instruction or to execute br.ia when
AR[BSPSTORE] != AR[BSP].
• Attempts to execute epc if PFS.ppl is less than PSR.cpl.
• Attempts to access interruption registers if PSR.ic is 1.
• Attempts to execute an itc or itr instruction if PSR.ic is 1.
• Attempts to allocate a stack frame larger than 96 registers, or with the
rotating region larger than the stack frame, or with the size of locals larger
than the stack frame, or specifying a qualifying predicate other than PR 0
on an alloc instruction.
• Attempts to execute instructions that are not supported by the processor.
• Attempts to execute a ldfp instruction with two odd-numbered physical FR
targets or two even-numbered physical FR targets.
• Attempts to access an application register from the wrong unit type.
• Attempts to execute a br.cloop, br.ctop, br.cexit, br.wtop, or
br.wexit other than in slot 2 of a bundle.
• Attempts to execute an alloc, flushrs or loadrs as other than the first
instruction in an instruction group. (The result of such an attempt is
undefined, and could result in an Illegal Operation fault, depending on the
processor implementation. See
page 1:44 for details).
• Attempts to execute a clrrrb, clrrrb.pr, cover, itc.d, itc.i, ptc.g or
ptc.ga instruction as other than the last instruction in an instruction group.
(The result of such an attempt is undefined, and may possibly result in an
Illegal Operation fault, depending on the processor See
"Undefined Behavior" on page 1:44
"Reserved and Ignored Registers and Fields" on page 1:23
Section 3.5, "Undefined Behavior" on
for details).
2:73.
Section 3.5,
and
2:193