Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 429

Data Key Miss vector (0x1c00)
Name
Cause For memory references (including IA-32), the PSR.dt bit is 1, the PSR.pk bit is 1, and
the access key from the TLB entry for the address referenced by a load, store, probe
(regular_form probe or probe.fault) or semaphore operation does not match any of
the valid protection keys. The RSE may cause this fault if PSR.rt is 1, the PSR.pk bit is
1, and the access key from the TLB entry for the address referenced by an RSE
mandatory load or store operation does not match any of the valid protection keys.
Interruptions on this vector:
IR Data Key Miss fault
Data Key Miss fault
IIP, IPSR, IIPA, IFS – are defined; refer to
Parameters
ITIR – The ITIR contains default translation information for the address contained in the
IFA. The access key field within this register is set to the region id value from the
referenced region register. The ITIR.ps field is set to the RR.ps field from the referenced
region register. All other fields are set to 0.
IFA – Faulting data address.
IIB0, IIB1 – If implemented, for Data Key Miss faults, the IIB registers contain the
instruction bundle pointed to by IIP. The IIB registers are undefined for IR Data Key
Miss faults. Please refer to
(IIB0-1 – CR26, 27)" on page 2:42
ISR – If the interruption was due to a non-access operation then the ISR.code bits
{3:0} are set to indicate the type of the non-access instruction; otherwise they are set
to 0. For mandatory RSE fill or spill references, ISR.ed is always 0. For IA-32 memory
references, the ISR.code, ed, ei, ni, ir, rs, sp, and na bits are 0. The value for the ISR
bits depend on the type of access performed and are specified below.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Notes Probe (regular_form probe or probe.fault) and the faulting variant of lfetch are the
only non-access instructions that will cause a data key miss fault.
Volume 2, Part 1: Interruption Vector Descriptions
Section 3.3.5.10, "Interruption Instruction Bundle Registers
0 0
0
page 2:165 for a detailed description.
for details on the IIB registers.
ed
8 7 6 5 4 3 2
0 code{3:0}
ei so ni ir rs sp na r w 0
1 0
2:181