Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 431
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Instruction Access-Bit vector (0x2400)
Name
Cause
For instruction fetches (including IA-32), the access bit (TLB.a) in the TLB entry for this
page is 0, and an instruction on the page is referenced.
Interruptions on this vector:
Instruction Access Bit fault
Parameters
IIP, IPSR, IIPA, IFS – are defined; refer to
ITIR – The ITIR contains default translation information for the address contained in the
IFA. The access key field within this register is set to the region id value from the
referenced region register. The ITIR.ps field is set to the RR.ps field from the referenced
region register. All other fields are set to 0.
IFA – The virtual address of the bundle or the 16 byte aligned IA-32 instruction address
zero extended to 64-bits.
IIB0, IIB1 – If implemented, the IIB registers are undefined. Please refer to
Section 3.3.5.10, "Interruption Instruction Bundle Registers (IIB0-1 – CR26, 27)" on
page 2:42
ISR – The ISR.ei bits are set to indicate which instruction caused the exception. For
IA-32 memory references the ISR.ei and ni bits are 0. The defined ISR bits are specified
below.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Notes
The fault can only occur when PSR.it is 1 on an instruction reference (including IA-32).
Software uses this fault for memory management page replacement algorithms. The
PSR.ia bit can be used to suppress this fault for one executed instruction.
Volume 2, Part 1: Interruption Vector Descriptions
for details on the IIB registers.
0
0
0
page 2:165
for a detailed description.
8
0
0
ei
0 ni 0 0 0 0 0 0 1
7
6
5
4
3
2
1
0
2:183
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