Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 587

When this optimization is enabled, execution of rsm and ssm instructions
PSR.vm==1 and system mask equal to zero (0x0), will not intercept to the VMM unless
a fault condition is detected (see
A virtual external interrupt is raised if the virtual highest priority pending interrupt
(vhpi) is unmasked by the new vpsr.i and vtpr. If the virtual highest priority pending
interrupt (vhpi) is still masked by the new vpsr.i or vtpr, no virtual external interrupt will
be raised. Note that execution of MOV-to-PSR instructions with PSR.vm==1 always
results in a virtualization intercept no matter which PSR bits are modified.
When this optimization is enabled, execution of rsm and ssm instructions
PSR.vm==1, which modify any bits in addition to vpsr.i result in a virtualization
intercepts. No virtual external interrupts are raised and the VMM is responsible for
delivering a virtual external interrupt if the virtual highest priority pending interrupt
(vhpi) is unmasked.
When this optimization is enabled, execution of a MOV-from-CR instruction, with
PSR.vm==1, targeting vtpr reads the most recent value, unless a fault condition is
detected (see
When this optimization is enabled, on execution of MOV-to-TPR instructions with
PSR.vm==1, vtpr will be updated with the new value without handling off to the VMM,
unless a fault condition is detected (see
interrupt is raised if the virtual highest priority pending interrupt (vhpi) is unmasked by
the new vpsr.i and vtpr. No virtual external interrupt is raised if the virtual highest
priority pending interrupt is still masked by vpsr.i or vtpr.
When this optimization is enabled, after completion of an instruction with PSR.vm==1
which modifies vtpr or vpsr.i (if the instruction completes without an intercept), a
determination is made as to whether the new state unmasks the virtual highest priority
pending interrupt. If it does, then a virtual external interrupt will be raised and the VMM
will be entered on the Virtual External Interrupt vector. See
the detection of virtual external interrupts.
Table 11-27. Detection of Virtual External Interrupts
vhpi <= (!vpsr.i << 5 | vtpr.mmi <<4 | vtpr.mic)
Synchronization is required when this optimization is enabled, see
details.
When this optimization is enabled, certain VPD state is accessed, as described in
Table 11-16, "Virtual Processor Descriptor (VPD)" on page
Table 11-28. Synchronization Requirements for Virtual External Interrupt
vtpr
vpsr.i
vhpi
Volume 2, Part 1: Processor Abstraction Layer
Table 11-29 for details).
Condition
vhpi > (!vpsr.i << 5 | vtpr.mmi <<4 | vtpr.mic)
Optimization
VPD Resource
Table 11-29 for details).
Table 11-29 for details). A virtual external
No – virtual highest priority pending interrupt
is still masked.
Yes – virtual highest priority pending
interrupt is unmasked.
Synchronization Required
Read, Write
Read, Write
Write
1
, with
1
, with
Table 11-27 for details on
Virtual External Interrupt
Table 11-28 for
2:326.
2:339