Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 370

Table 5-9.
Register
CR64
CR65
CR66
CR67
CR68
CR69
CR70
CR71
CR72
CR73
CR74
CR80
CR81
5.8.3.1 Local ID (LID – CR64)
The LID register contains the processor's local interrupt identifier. Two fields (id and
eid) serve as the processor's physical name for all interrupt messages (external
interrupts, INITs, and PMIs). LID is loaded by firmware during platform initialization
based on the processor's physical location within the system. Processors receiving an
interrupt message on the system interconnect may or may not compare their id/eid
fields with the target address for the interrupt message, depending on the type of
system interconnect. If this comparison is performed, then a match would indicate that
the interrupt received was intended for this processor. In case of no comparison,
processors use other system topology mechanisms to determine the correct target of
the interrupt message.
The LID register fields are either read-only or read-write. Details of the
programmability of these fields is communicated by PAL at PALE_RESET handoff (see
Section 11.2.2, "PALE_RESET Exit State" on page 2:289
always return a value of 0. Writes to read-only bits are ignored. To ensure that future
arriving interrupts see the updated LID value by a given point in program execution,
software must perform a data serialization operation after a LID write and prior to that
point. The Local ID fields are defined in
Figure 5-6.
63
Table 5-10.
Field
id/eid
2:122
External Interrupt Control Registers
Name
LID
IVR
TPR
EOI
IRR0
IRR1
IRR2
IRR3
ITV
PMV
CMCV
LRR0
LRR1
Local ID (LID – CR64)
ignored
32
Local ID Fields
Bits
31:16 The low order bits of id correspond to a unique, geographically significant address of
the processor on the local system bus. The eid field and the higher order bits of the id
field correspond to a unique address of the local system bus within the entire system.
These fields are initialized by platform firmware to an implementation-dependent value
and should not be modified by software. The two fields corresponds to physical
address bits{19:4} of the inter-processor interrupt message.
Description
Local ID
External Interrupt Vector Register (read only)
Task Priority Register
End Of External Interrupt
External Interrupt Request Register 0 (read only)
External Interrupt Request Register 1 (read only)
External Interrupt Request Register 2 (read only)
External Interrupt Request Register 3 (read only)
Interval Timer Vector
Performance Monitoring Vector
Corrected Machine Check Vector
Local Redirection Register 0
Local Redirection Register 1
for details). Read-only LID bits
Figure 5-6 and Table
32 31 24 23
id eid
8 8
Description
5-10.
16 15
reserved
16
Volume 2, Part 1: Interruptions
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