Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 631

Figure 11-9.
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• tid Thread id: The thread identifier of the logical processor for which information
–
is being returned. This value will be unique on a per core basis.
• rv Reserved
–
• cid Core id: The core identifier of the logical processor for which information is
–
being returned. This value will be unique on a per physical processor package basis.
• rv Reserved
–
There is no guarantee that the core id's and thread id's will be contiguous on a given
physical processor package.
Figure 11-10. Layout of proc_n_cache_info2 Return Value
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• la Logical address: geographical address of the logical processor for which
–
information is being returned. This is the same value that is returned by the
PAL_FIXED_ADDR procedure when it is called on the logical processor.
• rv Reserved
–
This procedure must be supported on all implementations that contain more than one
logical processor on a physical processor package and returns an unimplemented
procedure error code otherwise.
Volume 2, Part 1: Processor Abstraction Layer
Layout of proc_n_cache_info1 Return Value
rv
rv
rv
PAL_CACHE_SHARED_INFO
8
tid
cid
8
la
rv
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
2:383