Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 287

faulting instruction and IIP points to the first byte of the faulting instruction, or (2) for
faults on the second page, IFA contains the bundle address of the second virtual page
and IIP points to the first byte of the faulting IA-32 instruction.
The IFA also specifies a translation's virtual address when a translation entry is inserted
into the instruction or data TLB. See
and "Translation Insertion Format" on page 2:53
Figure 3-11, all 64-bits of the IFA must be implemented regardless of the size of the
virtual and physical space supported by the processor model (see
Address Bits" on page
raise an Unimplemented Data Address fault if an unimplemented virtual address is
used.
Figure 3-11.
63
3.3.5.5 Interruption TLB Insertion Register (ITIR – CR21)
The ITIR receives default translation information from the referenced virtual region
register on a virtual address translation fault. See
page 2:165
virtual address translation parameters on an insertion into the instruction or data TLB.
See "Translation Instructions" on page 2:60
and Table 3-8
Figure 3-12.
63
Table 3-8.
Field
rv/ci
ps
key
Volume 2, Part 1: System State and Programming Model
2:73). In some implementations, a mov to IFA instruction may
Interruption Faulting Address (IFA – CR20)
for the fault conditions that set the ITIR. The ITIR provides additional
define the ITIR fields.
Interruption TLB Insertion Register (ITIR)
rv/ci
32
ITIR Fields
Bits
63:32, Reserved / Check on Insert – On a read these fields may return zeros or the value last
written to them. If a non-zero value is written, a Reserved Register/Field fault may be
1:0
raised on the mov to ITIR instruction. If not, a subsequent TLB insert will raise a
Reserved Register Field fault depending on other parameters to the insert.
"Translation Insertion Format" on page 2:53.
these fields are set to zero.
7:2 Page Size – On a TLB insert, specifies the size of the virtual to physical address
mapping. If an unsupported page size is written, a Reserved Register/Field fault may be
raised on the mov to ITIR instruction. If not, a subsequent TLB insert will raise a
Reserved Register/Field fault.
instruction or data translation fault, this field is set to the accessed region's page size
(RR.ps).
31:8 Protection Key – On a TLB insert specifies a protection key that uniquely tags
translations to a protection domain. If non-zero values are written to unimplemented
protection key bits, a Reserved Register/Field fault may be raised on the mov to ITIR
instruction. If not, a subsequent TLB insert will raise a Reserved Register/Field fault
depending on other parameters to the insert.
page 2:53. On an instruction or data translation fault, this field is set to the accessed
Region Identifier (RR.rid).
"Interruption Vector Descriptions" on page 2:165
for usages of the IFA. As shown in
IFA
64
"Interruption Vector Descriptions" on
for ITIR usage information.
32 31
key
24
Description
On an instruction or data translation fault,
See "Translation Insertion Format" on page 2:53.
See "Translation Insertion Format" on
"Unimplemented
0
Figure 3-12
8 7 2 1 0
ps rv/ci
6 2
See
On an
2:39