Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 271

3.3.2 Processor Status Register (PSR)
The PSR maintains the current execution environment. The PSR is divided into four
overlapping sections (See
(PSR{23:0}), the lower half (PSR{31:0}), and the entire PSR (PSR{63:0}). PSR fields
are defined in
field and the state of the field after an interruption.
Figure 3-2.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
rv
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
The PSR instructions and their serialization requirements are defined in
These instructions explicitly read or write portions of the PSR. Other instructions also
read and write portions of the PSR as described in
Table 3-1.
Mnemonic
sum imm
rum imm
mov psr.um = r
mov r
1
ssm imm
rsm imm
mov psr.l = r
mov r
1
bsw.0, bsw.1
vmsw.0, vmsw.1
rfi
a. Based upon the resource being serialized, use data or instruction serialization.
b. All other bits of the PSR read as zero.
The user mask, PSR{5:0}, can be set and cleared by the Set User Mask (sum), Reset
User Mask (rum) and Move to User Mask (mov psr.um=) instructions at any privilege
level. For user mask modifications by sum, rum and mov, the processor ensures all side
effects are observed before subsequent instruction groups.
Volume 2, Part 1: System State and Programming Model
Figure
Table 3-2 along with serialization requirements for modification of each
Processor Status Register (PSR)
rt tb lp db si di pp sp dfh dfl dt rv pk i
rv
Processor Status Register Instructions
Description
Set user mask
from immediate
Reset user
mask from
immediate
Move to user
2
mask
Move from user
= psr.um
mask
Set system
mask from
immediate
Reset system
mask from
immediate
Move to lower
2
PSR
Move from PSR GR[r
= psr
Bank switch
Virtual machine
switch
Return From
Interruption
3-2): user mask bits (PSR{5:0}), system mask bits
system mask
ic
vm ia bn ed
Table 3-2
Operation
PSR{5:0}  PSR{5:0} | imm
PSR{5:0}  PSR{5:0} & ~imm
PSR{5:0}  GR[r
]
2
] PSR{5:0}
GR[r
1
PSR{23:0}  PSR{23:0} | imm
PSR{23:0}  PSR{23:0} &~imm
PSR{31:0}  GR[r
]
2
] PSR{36:35,31:0}
1
PSR{44} 0or 1
PSR{46} 0or 1
PSR{63:0}  IPSR
user mask
8 7 6 5 4 3
rv mfh mfl ac up be rv
36 35 34 33 32
ri ss dd da id it mc is
Table 3-1.
and Table 5-2.
Instr. Serialization
Type Required
M implicit
M implicit
M implicit
M none
M data/inst
M data/inst
M data/inst
b
M none
B implicit
B implicit
B implicit
2 1 0
cpl
a
a
a
2:23