Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 523

10.9 Interruption Model
Within the Itanium System Environment, all interruptions originating out of the IA-32 or
Itanium instruction sets are delivered to Itanium architecture-based Interruption
Handlers within the Itanium architecture-based operating system. Virtual memory
management faults, machine checks, and external interrupts are always delivered to
Itanium architecture-based interruption handlers regardless of the instruction set
running at the time of the interruption. IA-32 exceptions, control transfers through
gates, task switches, and accesses to sensitive IA-32 system resources are intercepted
into Itanium architecture-based interruption handlers. Using these intercepts, Itanium
architecture-based software can implement specific policies with regard to that
resource. Policies may include virtualization, emulation of an IA-32 opcode or memory
access, or various permission policies.
In general, if an interruption is independent of the executing instruction set (such as an
external interruption or TLB fault) common Itanium architecture-based handlers are
invoked. For classes of exceptions and intercept conditions that are specific to the IA-32
instruction set, three special Itanium architecture-based software handlers are invoked
to deal with IA-32 instruction set interruptions.
handlers defined to support IA-32 events. See
Definitions" on page 2:213
Table 10-8.
Handler
IA_32_Intercept
IA_32_Exception
IA_32_Interrupt
This grouping of interruption handlers simplifies software handlers such that they do
not need to be concerned with behavior of both IA-32 and Itanium instruction sets.
Interruption registers (defined in
point of interruption. For IA-32 exceptions, ISR contains IA-32 defined error codes and
vector numbers as defined by the Intel
Developer's Manual. IA-32 instruction set related exceptions and software
interruptions vector directly through the interruption mechanism defined by the
Itanium architecture without consulting the IA-32 IDT or performing any memory stack
pushes.
10.9.1 Interruption Summary
Table 10-9
Itanium architecture-based interruption handlers within the Itanium System
Environment. See
Table 10-9.
IA-32
Vector
IA-32 Defined Interruptions
0 IA_32_Exception (Divide)
®
Volume 2, Part 1: Itanium Architecture-based Operating System Interaction Model with IA-32 Applications
for details on these interruption handlers.
IA-32 Interruption Vector Summary
Intercepted IA-32 instructions, I/O, system flag manipulation and gate transfers.
IA-32 instruction set generated exceptions.
IA-32 instruction set generated software interrupts
summarizes the set of all IA-32 interruptions and how they are mapped to
Chapter 9 and
IA-32 Interruption Summary
®
Itanium Architecture-based
Interruption Handler
Table 10-8
Section 9.2, "IA-32 Interruption Vector
Description
Chapter 3) record the state of IA-32 execution at the
®
64 and IA-32 Architectures Software
Chapter 8 for a detailed definition of each interruption.
ISR ISR
Vector Code
0 0
shows the three interruption
Description
IA-32 divide by zero fault.
2:275