Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 464

IA_32_Exception (Debug) – Data Breakpoint, Single Step, Taken
Name
Branch Trap
Cause The Itanium architecture debug facilities triggered an IA-32 data breakpoint,
single-step or branch trap. In the Itanium System Environment, IA-32 Mov SS or Pop
SS single step and data breakpoint traps are NOT deferred to the next instruction. Refer
to the Intel
complete definition of this trap.
Parameters IIPA – virtual address of the trapping IA-32 instruction (zero extended to 64-bits) if
there was a taken branch trap. On jmpe taken branch traps IIPA contains the address of
the jmpe instruction. For all other trap events, IIPA is undefined.
IIP – next Itanium instruction address or the virtual IA-32 instruction address zero
extended to 64-bits.
ISR.vector – 1.
ISR.code – Trap Code, indicates Concurrent Single Step, Taken Branch, Data Breakpoint
Trap events.
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64 and IA-32 Architectures Software Developer's Manual for a
rv 1
rv
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trap_code
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Volume 2, Part 1: IA-32 Interruption Vector Descriptions
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