Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 832

7.2 Unsupported Data Reference Handler
Processors based on the Itanium architecture do not support all types of memory
references to all memory attributes. In particular:
• Semaphore operations to uncacheable memory are not supported. For details
consult
page
• A 10-byte memory access, e.g. ldfe or stfe, to uncacheable memory are not
supported by all implementations.
The handler for 10-byte memory accesses must go through the following steps to
emulate the ldfe or stfe instructions:
• Determine that the opcode at the faulting address is an ldfe or stfe. On
control-speculative flavors of these instructions (ldfe.s or ldfe.sa) processor
hardware always defers the unsupported data reference fault. In other words,
software does not have to emulate control-speculative fault deferral.
• If the instruction is an advanced load ldfe.a then the emulation handler should
invalidate the ALAT entry of the appropriate floating-point target register using the
invala.e instruction. Furthermore, a zero should be returned in the floating-point
target register.
• If the instruction is a regular ldfe or stfe, then software must emulate the load or
store behavior of the instruction taking the appropriate faults if necessary.
• If the instruction is the base register update form, update the appropriate base
register.
A number of these steps may require the use of self-modifying code to patch
instructions with the appropriate operands (for example, the target register of the
inval.e must be patched to the destination register of the ldfe or stfe). See
Section 2.5, "Updating Code Images" on page 2:531
7.3 Illegal Dependency Fault
The Itanium instruction sequencing rules specify that, generally speaking, instructions
within an instruction group are free of dependencies as described in
"Instruction Sequencing Considerations" on page
anytime a program violates read-after-write (RAW), write-after-write (WAW) or
write-after-read (WAR) resource dependency rules within an instruction group.
As Section 3.4.4, "Processor Behavior on Dependency Violations" on page 1:44
describes, an implementation may provide hardware to detect and report dependency
violations. It is important to note that the presence and capabilities of such hardware is
implementation specific. A processor based on the Itanium architecture reports
dependency violations through the General Exception Vector with an ISR.code of 8.
It is recommended that operating systems log the dependency violation and then
terminate the offending application, as hardware behavior is undefined when a
dependency violation occurs.
2:584
Section 2.1.3.2, "Behavior of Uncacheable and Misaligned Semaphores" on
2:509.
for more information.
1:39. A dependency violation occurs
Volume 2, Part 2: Instruction Emulation and Other Fault Handlers
Section 3.4,