Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 320

In the sign-extension model, software ensures that the upper 32-bits of a virtual
address are always equal to bit 31. Address computations use the add, shladd, and sxt
instructions. This model splits the 32 bit address space into two halves that are spread
31
into 2 bytes of virtual regions 0 and 7 within the 64-bit virtual address space. In this
model, regions 2 to 6 are accessible only by 64-bit addressing.
The pointer "swizzling" model performs address computations with the addp4, and
shladdp4 instructions. These instructions generate a 32-bit address within the 64-bit
virtual address space as shown in
divided into 4 sections that are spread into 2
64-bit virtual address space. In this model, regions 4 to 7 are accessible only by 64-bit
addressing.
Figure 4-17.
63
In the pointer "swizzling" model, mappings within each region do not necessarily start
at offset zero, since the upper 2-bits of a 32-bit address serve both as the virtual region
number and an offset within each region. Virtual address bits{62:61} do not participate
in the address addition, therefore some regions may be effectively larger than 2
due to the addition of a 32-bit offset and lack of a carry into bits{62:61}. Note that the
conversion is non-destructive: a converted 64-bit pointer can be used as a 32-bit
pointer. Flat 31 or 32 bit address spaces can be constructed by assigning the same
region identifier to contiguous region registers. Branches into another 2
are performed by first calculating the target address in the 32-bit virtual space and
then converting to a 64-bit pointer by addp4. Otherwise, branch targets will extend
above the 2
4.1.10 Virtual Aliasing
Virtual aliasing (two or more virtual pages mapped to the same physical page) is
functionally supported for memory references (including IA-32), however performance
may be degraded on some processor models where the distance between virtual aliases
is less than 1 MB. To avoid any possible performance degradation, software is advised
to use aliases whose virtual addresses differ by an integer multiple of 1 MB. The
processor ensures cache coherency and data dependencies in the presence of an alias.
Stores using a virtual alias followed by a load with another alias to the same physical
location see the effects of prior stores to the same physical memory location.
To support advanced loads in the presence of a virtual alias, the processor ensures that
the Advanced Load Address Table (ALAT) is resolved using physical addresses and is
coherent with physical memory. For details, please refer to
the ALAT and Related Instructions" on page
2:72
32-bit Address Generation using addp4
Base
32 31 30 29
63 62 61 60
0
000000
30
byte boundary within the originating region.
Figure 4-17. The 32-bit virtual address space is
30
bytes of virtual regions 0 to 3 within the
0
63
+
32 31
1:65.
Volume 2, Part 1: Addressing and Protection
Offset
32 31
0
30
bytes
30
-byte region
"Detailed Functionality of
0