Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 868

The PAL firmware provides information about the performance monitor registers that
are implemented on the processor through the PAL_PERF_MON_INFO PAL call.
Information provided by the PAL includes bit masks which indicate which PMC/PMD
registers are implemented on this processor model, as well as the implemented number
of generic PMC/PMD pairs, and the counter width of the generic counters.
12.2 Operating System Support
The monitoring mechanisms discussed in the previous section support two performance
monitoring usage models that need support from an Itanium architecture-based
operating system.
• Per Thread/Process Event Monitoring
To monitor processor events per thread the operating system needs to save and restore
performance monitor state at thread/process context switches. This save/restore of
PMC and PMD registers only needs to be done for monitored threads. The effect of the
save/restore is that when a monitored thread is running, PMD reads will reflect events
for the monitored thread/process only.
Switch" defines the steps required for per-thread context switch of performance
monitors. It is worth noting that the PMC/PMD masks returned from
PAL_PERF_MON_INFO indicate which PMC/PMD registers are implemented. The context
switch routine can use the mask to save/restore implemented monitors without
knowing the function of the monitors.
• System Wide Event Monitoring
To monitor processor events system wide (across all processes and the operating
system kernel itself), a monitor must be enabled continuously across all contexts. This
can be achieved by configuring a privileged monitor (PMC.pm=1), and by ensuring that
PSR.pp and DCR.pp remain set for the duration of the monitor session. Since the
operating system typically reloads PSR and possibly DCR on context switch, this
requires the operating system to set PSR.pp and DCR.pp for all contexts that are active
during the monitoring session. One way to accomplish this is to have code in the
context switch routine to always set PSR.pp and DCR.pp when system wide monitoring
is in effect. Another technique is to set the initial state for all new threads/processes to
PSR.pp=1, PSR.up=0, PSR.sp=0 and DCR.pp=1. Setting the per thread PSR and DCR
in this way ensures that privileged monitors will be enabled across all contexts. When
system wide monitoring is in effect, PSR.pp, DCR.pp as well as the PMC and PMD
registers should not be altered by the context switch routine.
To support both per thread and system wide monitoring, the operating system needs to
be aware which type of monitoring is being performed at any given moment. If per
thread/process monitoring is active, then the operating system must save/restore
monitor state for monitored threads. If system wide monitoring is active, then the
operating system must ensure that PSR.pp and DCR.pp remain set.
The preferred approach for performance monitoring is for Itanium architecture-based
operating systems to provide a set of kernel mode services that allow performance
monitoring software to be implemented in a loadable device driver. Such a loadable
device driver can support various usage monitoring models, can be adapted to
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Section 7.2.4.2, "Performance Monitor Context
Volume 2, Part 2: Performance Monitoring Support