Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 787

instruction address translation is disabled, the IVA register should contain the physical
address of the base of the IVT. Software must further ensure that instruction and
memory references from low-level interruption handlers do not generate additional
interruptions until enough state has been saved and interruption collection can be
re-enabled.
There are many more interruptions than there are interruption vectors in the IVT. As
specified in
between interruptions and interruption vectors. The interruptions that share a common
interruption vector (and hence, the code for an interruption handler) can determine
which interruption occurred by reading the Interruption Status Register (ISR) control
register. See
Interruption Vector Descriptions"
interruption.
3.3 Interruption Handlers
3.3.1 Execution Environment
As defined in
processor automatically clears the PSR.i and PSR.ic bits when an interruption is
delivered. This disables external interrupts and interrupt state collection, respectively.
PMI delivery is also disabled while PSR.ic is 0; other PAL-based interruptions can be
delivered at any point during the execution of the interruption handler, regardless of the
state of PSR.i and PSR.ic.
In addition to clearing the PSR.i and PSR.ic bits, the processor also automatically clears
the PSR.bn bit when an interruption is delivered, switching to bank 0 of general
registers GR16 - GR31. This provides the interruption handler with its own set of
registers which can be used without spilling any of the interrupted context's register
state, effectively saving GR16 - GR31 of the interrupted context. (This assumes PSR.bn
is 1 at the time of interruption; see
page 2:546
As specified in
of bank 0 should not be used while PSR.ic is 1. By firmware convention, PAL-based
interruption handlers may use these registers without preserving their values when
PSR.ic is 1. When PSR.ic is 0, software may safely use GR24 - GR31 of bank 0 as
scratch register.
Several other PSR bits and the RSE.CFLE are modified by the hardware when an
interruption is delivered.
interruption handlers operate in, and what each PSR bit and the RSE.CFLE values mean
for the interruption handler.
Volume 2, Part 2: Interruptions and Serialization
Section 5.6, "Interruption Priorities"
Chapter 8, "Interruption Vector Descriptions"
for details of the specific ISR settings for each unique
Section 5.5, "IVA-based Interruption Handling" on page
for how to deal with the case where PSR.bn is 0 at the time of interruption.)
Section 3.3.7, "Banked General Registers" on page
Table 3-1
there is a many-to-one relationship
Section 3.4.3, "Nested Interruptions" on
summarizes the execution environment that
and Chapter 9, "IA-32
2:101, the
2:42, GR24 - GR31
2:539