Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 498

Table 10-4.
Field
CR4.VME
CR4.PVI
CR4.TSD
CR4.DE
CR4.PSE
CR4.PAE
CR4.MCE
CR4.PGE
2:250 Volume 2, Part 1: Itanium
IA-32 Control Register Field Definition (Continued)
® ®
Intel Itanium State
CFLG.vme 32
CFLG.pvi 33
CFLG.tsd 34
CFLG.de 25
CFLG.pse 36
CFLG.pae 37
CFLG.mce 38
CFLG.pge 39
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Architecture-based Operating System Interaction Model with IA-32 Applications
Bits
IA-32 Virtual Machine Extension and Protected
Mode Virtual Interrupt Enable: These bits control
the VM86 VME extensions and Protected Mode
Virtual Interrupt extensions defined in the Intel
and IA-32 Architectures Software Developer's
Manual for STI, CLI and PUSHF. These bits have
no effect on Intel Itanium instructions. This bit is
supported in both the IA-32 and Intel Itanium
System Environments.
Time Stamp Disable: IA-32 RDTSC user level reads
of the Time Stamp Counter are enabled when
CR4.tsd when zero. Otherwise execution of the
RDTSC instruction results in a GPFault. CFLG.tsd
is ignored by Intel Itanium instructions. This bit is
supported in both the IA-32 and Intel Itanium
System Environments. See the Intel
IA-32 Architectures Software Developer's
Manual for details on these bits.
Debug Extensions: In the Intel Itanium System
Environment, this bit is ignored by IA-32 or Intel
Itanium references to the I/O port space. This bit is
provided as storage for compatibility purposes. This
bit is supported as defined in the Intel
IA-32 Architectures Software Developer's
Manual for the IA-32 System Environment.
Page Size Extensions: In the Intel Itanium System
Environment, this bit is ignored by IA-32 or Intel
Itanium references. In the IA-32 System
Environment, this bit enables 4M-byte page
extensions for IA-32 paging. Modification of this bit
by Itanium architecture-based code does have any
side effects such as flushing the TLBs.
Physical Address Extensions: In the IA-32 System
Environment, this bit enables IA-32 Physical
Address Extensions for IA-32 paging This bit is
ignored in the Intel Itanium System Environment.
Modification of this bit by Itanium
architecture-based code does have any side effects
such as flushing the TLBs.
Machine Check Enable: This bit is ignored in the
Intel Itanium System Environment. This bit is
provided as storage for compatibility purposes. This
bit is supported as defined in the Intel
IA-32 Architectures Software Developer's
Manual for the IA-32 System Environment.
Paging Global Enable: This bit is ignored in the Intel
Itanium System Environment. This bit is provided as
storage for compatibility purposes. This bit is
supported as defined in the Intel
Architectures Software Developer's Manual for
the IA-32 System Environment, where this bit
enables global pages for the IA-32 paging.
Modification of this bit by Itanium
architecture-based code does have any side effects
such as flushing the TLBs.
Description
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64
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64 and
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64 and
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64 and
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64 and IA-32