Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 865

As a result of the spreading-out of the I/O ports into individual 4KB pages, Itanium
architecture-based operating system code can control IA-32 IN, OUT instruction and
IA-32 or Itanium load/store accessibility to blocks of 4 virtual I/O ports using the TLBs.
This allows Itanium architecture-based operating systems to securely map devices that
inhabit the I/O port space to different Itanium architecture-based device drivers or to
user-space Itanium architecture-based applications.
Itanium architecture-based operating systems must ensure that the I/O port space is
always mapped as uncacheable memory, and that Itanium architecture-based software
only issues aligned 1, 2 or 4 byte references to I/O port space, otherwise device
behavior is undefined.
When porting an IA-32 device driver to the Itanium architecture it can be useful to
emulate the behavior of IA-32 IN and OUT instructions. The following code examples
should be used for this purpose, since they enforce the strict memory ordering and
platform acceptance requirements that IA-32 IN and OUT instructions are subject to.
The following Itanium architecture-based assembly code outb (out byte) and inb (in
byte) examples assume that the io_port_base is the virtual address mapping pointer
set up by the IA_64 operating system. An mf.a instruction is used to verify acceptance
by the platform before returning to the calling routine. Interrupts would expected to be
disabled if these routines are called from user mode. This is for possible issues with
process migration after servicing an interrupt.
//
// void outb(unsigned char *io_port,unsigned char byte)
//
//Output a byte to an I/O port.
//
ENTRY(outb)
base_addr = r16
port_addr = r17
port_offset = r18
mask = r19
alloc
movl
extr.u
mov
;;
ld8
shl
and
;;
add
;;
mf
add
;;
st1.rel [port_addr] = in1
mf.a
mf
br.ret.spnt.few rp
END(outb)
//
// unsigned char inb(unsigned char *io_port)
//
// Input a byte from an I/O port.
//
ENTRY(inb)
base_addr = r16
port_addr = r17
port_offset = r18
Volume 2, Part 2: I/O Architecture
r13 = ar.pfs, 2, 0, 0, 0
base_addr = io_port_base
port_offset = in0, 2, 14
mask = 0xfff
port_addr = [base_addr]
port_offset = port_offset, 12
in0 = mask, in0
port_offset = port_offset, in0
port_addr = port_addr, port_offset
// 2 in, 0 local, 0 out, 0 rot
2:617