Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 582

• IRRs: The contents of IRRs are not changed by PAL. Incoming interruptions
may change the contents.
• IFS: IFS is unchanged from the time of the interruption.
• IIP: Contains the value of IP at the time of the interruption.
• IPSR: Contains the value of PSR at the time of the interruption.
• RRs: The contents of all region registers are preserved from the time of the
interruption.
• PKRs: The contents of all protection key registers are preserved from the time of
the interruption.
• DBRs/IBRs: The contents of all breakpoint registers are preserved from the time of
the interruption.
• PMCs/PMDs: The contents of the PMC registers are preserved from the time of the
virtualization intercept. The contents of the PMD registers are not modified by PAL
code, but may be modified if events being monitored are encountered. The
performance counters will be frozen if specified by the VMM through a parameter of
PAL_VP_INIT_ENV procedure.
• Cache: The processor internal cache is not specifically modified by PAL handler but
may be modified due to normal cache activity of running the handler code.
• TLB: The TRs are unchanged from the time of the interruption.
Table 11-22. PAL Virtualization Intercept Handoff Cause (GR24)
Value
1 toAR
2 toARimm
3 fromAR
4 toCR
5 fromCR
6 toPSR
7 fromPSR
8 itc_d
9 itc_i
10 toRR
11 toDBR
12 toIBR
13 toPKR
14 toPMC
15 toPMD
16 itr_d
17 itr_i
18 fromRR
19 fromDBR
20 fromIBR
21 fromPKR
22 fromPMC
23 fromCPUID
24 ssm
25 rsm
26 ptc_l
2:334
Cause
Due to MOV-to-AR instruction.
Due to MOV-to-AR-imm instruction.
Due to MOV-from-AR instruction.
Due to MOV-to-CR instruction.
Due to MOV-from-CR instruction.
Due to MOV-to-PSR instruction.
Due to MOV-from-PSR instruction.
Due to itc.d instruction.
Due to itc.i instruction.
Due to MOV-to-RR instruction.
Due to MOV-to-DBR instruction.
Due to MOV-to-IBR instruction.
Due to MOV-to-PKR instruction.
Due to MOV-to-PMC instruction.
Due to MOV-to-PMD instruction.
Due to itr.d instruction.
Due to itr.i instruction.
Due to MOV-from-RR instruction.
Due to MOV-from-DBR instruction.
Due to MOV-from-IBR instruction.
Due to MOV-from-PKR instruction.
Due to MOV-from-PMC instruction.
Due to MOV-from-CPUID instruction.
Due to ssm instruction.
Due to rsm instruction.
Due to ptc.l instruction.
Description
Volume 2, Part 1: Processor Abstraction Layer