Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 439

Data Access Rights vector (0x5300)
Name
Cause For memory references (including IA-32), the PSR.dt bit is 1, and the access rights for
this page do not allow read access or do not allow read access at the current privilege
level for load and semaphore operations. The PSR.dt bit is 1, and the access rights for
this page do not allow write access or do not allow write access at the current privilege
level for store and semaphore operations.
The PSR.rt bit is 1, and the access rights for this page do not allow read access or do
not allow read access at the current privilege level for the RSE mandatory load
operation. The PSR.rt bit is 1, and the access rights for this page do not allow write
access or do not allow write access at the current privilege level for the RSE mandatory
store operation.
Interruptions on this vector:
IR Data Access Rights fault
Data Access Rights fault
Parameters IIP, IPSR, IIPA, IFS – are defined; refer to
ITIR – The ITIR contains default translation information for the address contained in the
IFA. The access key field within this register is set to the region id value from the
referenced region register. The ITIR.ps field is set to the RR.ps field from the referenced
region register. All other fields are set to 0.
IFA – Faulting data address.
IIB0, IIB1 – If implemented, for Data Access Rights faults, the IIB registers contain the
instruction bundle pointed to by IIP. The IIB registers are undefined for IR Data Access
Rights faults. Please refer to
Registers (IIB0-1 – CR26, 27)" on page 2:42
ISR – The value for the ISR bits depend on the type of access performed and are
specified below. For mandatory RSE fill or spill references, ISR.ed is always 0. For IA-32
memory references, ISR.code, ed, ei, ni, ir, rs, and sp bits are 0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Notes For probe.fault or lfetch.fault the ISR.na bit is set.
Volume 2, Part 1: Interruption Vector Descriptions
Section 3.3.5.10, "Interruption Instruction Bundle
0 0
0
page 2:165 for a detailed description.
for details on the IIB registers.
8
0
ed ei so ni ir rs sp na r w 0
7 6 5 4 3 2 1 0
code{3:0}
2:191