Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 488

conventions. Software should follow IA-32 and Itanium software calling conventions
for these registers.
• Shared: Shared registers contain values that have similar functionality in either
instruction set. For example, all Itanium control registers, debug registers are used
for memory references (including IA-32). The stack pointer (ESP) and instruction
pointer (IP) are also shared.
• Unmodified: These registers are not altered by IA-32 execution. Itanium
architecture-based code can rely on these values not being modified during IA-32
instruction set execution. The register will have the have the same contents when
entering the IA-32 instruction set and when exiting the IA-32 instruction set.
• Undefined: Registers marked as undefined may be used as scratch areas for
execution of IA-32 instructions. Software can not rely on the value of these
registers across an instruction set transition.
Table 10-1.
®
Intel
®
Itanium
Reg
Application Registers
EFLAG
CSD
SSD
CFLG
Kernel Registers
KR0
KR1
KR2
KR3-7
Banked General Registers
GR16-31
Control Registers
DCR
IFA, IIP,
IPSR, ISR,
IIM, IIPA,
ITIR, IHA,
IIB0-1, IFS,
IVA
PTA
ITM
2:240 Volume 2, Part 1: Itanium
IA-32 System Register Mapping
IA-32 Reg Convention
EFLAG
CSD
IA-32 state
SSD
CR0/CR4
b
IOBASE
c
TSSD IA-32 state
d
CR3/CR2
unmodified
unmodified
unmodified,
shared
shared
shared
shared
®
Architecture-based Operating System Interaction Model with IA-32 Applications
Size
32 IA-32 System/Arithmetic flags,
writes of some bits are conditioned by PSR.cpl and
EFLAG.iopl.
64 IA-32 code segment (register format)
IA-32 stack segment (register format)
64 IA-32 control flags, CR0=CFLG{31:0},
a
CR4=CFLG{63:32} , writable at PSR.cpl=0 only.
IA-32 virtual I/O port Base register
64 IA-32 TSS descriptor (register format)
IA-32 CR2=KR2{63:32}, CR3=KR2{31:0}
Intel Itanium preserved registers
Preserved for operating system use
Controls instruction set execution (including IA-32)
Intel Itanium interruption registers may be overwritten on
any TLB fault, interruption or exception encountered
during IA-32 or Intel Itanium instruction set execution.
64
Shared page table base for memory references
(including IA-32)
64
shared Intel Itanium interruption/timer resources
Description