Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 583

Table 11-22. PAL Virtualization Intercept Handoff Cause (GR24) (Continued)
Value
27 ptc_g
28 ptc_ga
29 ptr_d
30 ptr_i
31 thash
32 ttag
33 tpa
34 tak
35 ptc_e
36 cover
37 rfi
38 bsw_0
39 bsw_1
40 vmsw
41 probe
All Reserved
other
values
Figure 11-15. PAL Virtualization Intercept Handoff Opcode (GR25)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
b m
11.7.4 Virtualization Optimizations
After the PAL_VP_INIT_ENV procedure is called, execution of the virtualized
instructions listed in
PSR.vm==1 results in virtualization intercepts to the VMM. Virtualization optimizations
reduce overall virtualization overhead by allowing these instructions to execute, with
PSR.vm==1, without causing intercepts to the VMM. There are two types of
virtualization optimizations – global and local. Local virtualization optimizations are
further divided into virtualization accelerations and virtualization disables.
Global virtualization optimizations are specified during initialization of the virtual
environment (i.e., during PAL_VP_INIT_ENV). The specified optimizations are
applicable to all the virtual processors running in the virtual environment. See
11.7.4.1, "Global Virtualization Optimizations"
optimizations supported in the architecture.
Local virtualization optimizations are specified during the creation of the virtual
processor (i.e., during PAL_VP_CREATE). The optimization settings were specified in the
VPD and hence local to each virtual processor. The VMM can specify different local
optimization settings for different virtual processors. The two classes of local
virtualization optimizations are:
• Virtualization accelerations – Virtualization accelerations optimize the execution of
virtualized instructions by supporting fast access to the virtual instance of the
Volume 2, Part 1: Processor Abstraction Layer
Cause
Due to ptc.g instruction.
Due to ptc.ga instruction.
Due to ptr.d instruction.
Due to ptr.i instruction.
Due to thash instruction.
Due to ttag instruction.
Due to tpa instruction.
Due to tak instruction.
Due to ptc.e instruction.
Due to cover instruction.
Due to rfi instruction.
Due to bsw.0 instruction.
Due to bsw.1 instruction.
Due to vmsw instruction.
Due to probe instruction.
Reserved for future expansion.
Opcode {31:6}
Reserved
Table 3-10, "Virtualized Instructions" on page 2:44
Description
8 7 6
Opcode {40:32}
for details on the global virtualization
5 4 3 2 1 0
Reserved
with
Section
2:335