Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 329

a. Speculative or speculative advanced loads that cause deferred exceptions result in failed speculation. The
processor aborts the reference. If the target of the load is a GR, the processor sets the register's NaT bit to
one. If the target of the load is an FR, the processor sets the target FR to NaTVal. The processor performs all
other side-effects (such as post-increment).
b. Speculative or speculative advanced loads to limited or non-speculative memory pages result in failed
speculation. The processor aborts the reference. If the target of the load is a GR, the processor sets the
register's NaT bit to 1. If the target of the load is an FR, the processor sets the target FR to NaTVal. The
processor performs all other side-effects (such as post-increment).
c. Advanced loads to non-speculative memory pages always fail. The processor aborts the reference, sets the
target register to zero, and performs all other side-effects (such as post-increment).
4.4.6.1 Limited Speculation and the WBL Physical Addressing Attribute
Processors are allowed to reference limited speculation pages (WBL pages)
speculatively, in order to increase performance, but this speculation is limited to
prevent speculative references to 4Kbyte physical pages for which there is no actual
memory (which would cause spurious machine checks).
Processors must not make hardware-generated speculative references to a given WBL
4Kbyte page until a verified reference has been made. Processors may optionally
implement storage to hold the addresses of WBL 4Kbyte pages for which verified
references have been made, and may make subsequent hardware-generated
speculative references to these pages. Such pages are termed verified pages.
A verified reference is an instruction or data reference made to the page by an in-order
execution of the program; that is, a reference which would have been made had the
instructions from the program been fetched and executed one at a time. A
hardware-generated speculative reference does not constitute a verified reference.
Hardware-generated speculative references include:
• Instruction fetches when the processor has not yet determined whether prior
branches were predicted correctly
• Instruction fetches when the processor has not yet determined whether prior
instructions will raise faults or traps
• Data references by instructions when the processor has not yet determined
whether prior branches were predicted correctly
• Data references by instructions when the processor has not yet determined
whether prior instructions will raise faults or traps
• Hardware-generated instruction prefetch references
• Hardware-generated data prefetch references
• Eager RSE data references
For an instruction fetch to constitute a verified reference, it must only be determined
that an in-order execution of the program requires that the IP point to this address,
independent of whether the instruction at this address will subsequently take a fault or
interrupt.
For a data reference to constitute a verified reference, the instruction must meet one of
the following requirements:
• It executes without any fault or interrupt
• It takes an Unaligned Data Reference fault
• It takes a Data Debug fault
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