Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 262

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2.2 Intel
The Itanium System Environment is designed to support execution of Itanium
architecture-based operating systems running IA-32 or Itanium architecture-based
applications. IA-32 applications can interact with Itanium architecture-based operating
systems, applications and libraries within this environment. Both IA-32 application level
code and Itanium instructions can be executed by the operating system and user level
software. The entire machine state, including the IA-32 general registers and
floating-point registers, segment selectors and descriptors is accessible to Itanium
architecture-based code. As shown in
fully supported.
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Figure 2-2. Intel Itanium
Real Mode
IA-32 Real Mode
Instructions and
Segmentation
Interruption &
Intercepts
In the Itanium system environment, Itanium architecture operating system resources
supersede all IA-32 system resources. Specifically, the IA-32 defined set of control,
test, debug, machine check registers, privilege instructions, and virtual paging
algorithms are replaced by the Itanium architecture system resources. When IA-32
code is running on an Itanium architecture-based operating system, the processor
directly executes all performance critical but non-sensitive IA-32 application level
instructions. Accesses to sensitive system resources (interrupt flags, control registers,
TLBs, etc.) are intercepted into the Itanium architecture-based operating system. Using
this set of intervention hooks, an Itanium architecture-based operating system can
emulate or virtualize an IA-32 system resource for an IA-32 application, OS, or device
driver.
The Itanium system architecture features are presented in the following chapters:
• Chapter 3, "System State and Programming Model"
• Chapter 4, "Addressing and Protection"
• Chapter 5, "Interruptions"
• Chapter 6, "Register Stack Engine"
• Chapter 7, "Debugging and Performance Monitoring"
performance monitoring hooks.
• Chapter 8, "Interruption Vector Descriptions"
points.
2:14
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Itanium System Environment Overview
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System Environment
VM86
IA-32 VM86
Instructions and
Segmentation
Paging & Interruption
Handling in the
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Intel Itanium
defines the interrupt and exception architecture.
Figure 2-2, all major IA-32 operating modes are
Protected Mode
IA-32 PM
Instructions and
Segmentation
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Architecture
describes system resources.
describes the virtual memory architecture.
describes the register stack engine.
describes debug and
describes interruption handler entry
Volume 2, Part 1: Intel
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Intel Itanium
Architecture
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Intel Itanium
Instructions
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Itanium System Environment