System And Memory Overview; System Architecture - ST STM32F423 Reference Manual

System and memory overview

2 System and memory overview
2.1

System architecture

In STM32F413/423, the main system consists of 32-bit multilayer AHB bus matrix that
interconnects:
•
Six masters:
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• Seven slaves:
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The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in
54/1324
®
Cortex -M4 with FPU core I-bus, D-bus and S-bus
DMA1 memory bus
DMA2 memory bus
DMA2 peripheral bus
Internal Flash memory ICode bus
Internal Flash memory DCode bus
Main internal SRAM1 (256 KB)
Auxiliary internal SRAM2 (64 KB)
AHB1 peripherals including AHB to APB bridges and APB peripherals
AHB2 peripherals
FSMC / QuadSPI
Figure 1.
RM0430 Rev 8
RM0430