Multichannel Buffered Serial Port Timing - Texas Instruments TMS320C6712D User Manual

TMS320C6712D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS293 − OCTOBER 2005

MULTICHANNEL BUFFERED SERIAL PORT TIMING

timing requirements for McBSP
NO. NO.
2 t c(CKRX) Cycle time, CLKR/X
3 t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low
5 5 t su(FRH-CKRL) t su(FRH-CKRL) Setup time, external FSR high before CLKR low Setup time, external FSR high before CLKR low
6 6 t h(CKRL-FRH) t h(CKRL-FRH) Hold time, external FSR high after CLKR low Hold time, external FSR high after CLKR low
7 7 t su(DRV-CKRL) t su(DRV-CKRL) Setup time, DR valid before CLKR low Setup time, DR valid before CLKR low
8 8 t h(CKRL-DRV) t h(CKRL-DRV) Hold time, DR valid after CLKR low Hold time, DR valid after CLKR low
10 10 t su(FXH-CKXL) t su(FXH-CKXL) Setup time, external FSX high before CLKX low Setup time, external FSX high before CLKX low
11 11 t h(CKXL-FXH) t h(CKXL-FXH) Hold time, external FSX high after CLKX low Hold time, external FSX high after CLKX low
† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
§ The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for
communications between the McBSP and other device is 75 Mbps for 150 MHz CPU clock; where the McBSP is either the master or the slave.
Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP
communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 15 ns (67 MHz), whichever
value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 15 ns as the minimum CLKR/X clock cycle (by setting the
appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum
CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame
syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode
(R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
¶ This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
86
†‡
(see Figure 41)
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
−150
MIN
2P §
CLKR/X ext
0.5 * t c(CKRX) −1 ¶
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
UNIT UNIT
MAX
ns
ns
9
ns ns
1
6
ns ns
3
8
ns ns
0
3
ns ns
4
9
ns ns
1
6
ns ns
3