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ST STM32L4+ Series Reference Manual page 1719

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RM0432
50.2
USART main features
Full-duplex asynchronous communication
NRZ standard format (mark/space)
Configurable oversampling method by 16 or 8 to achieve the best compromise
between speed and clock tolerance
Baud rate generator systems
Two internal FIFOs for transmit and receive data
Each FIFO can be enabled/disabled by software and come with a status flag.
A common programmable transmit and receive baud rate
Dual clock domain with dedicated kernel clock for peripherals independent from PCLK
Auto baud rate detection
Programmable data word length (7, 8 or 9 bits)
Programmable data order with MSB-first or LSB-first shifting
Configurable stop bits (1 or 2 stop bits)
Synchronous master/slave mode and clock output/input for synchronous
communications
SPI slave transmission underrun error flag
Single-wire Half-duplex communications
Continuous communications using DMA
Received/transmitted bytes are buffered in reserved SRAM using centralized DMA.
Separate enable bits for transmitter and receiver
Separate signal polarity control for transmission and reception
Swappable Tx/Rx pin configuration
Hardware flow control for modem and RS-485 transceiver
Communication control/error detection flags
Parity control:
Interrupt sources with flags
Multiprocessor communications: wakeup from Mute mode by idle line detection or
address mark detection
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Transmits parity bit
Checks parity of received data byte
RM0432 Rev 6
1719/2301
1858

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