Flash Read Access Latency; Table 12. Number Of Wait States According To Flash Memory Clock (Hclk) Frequency - ST STM32G0 1 Series Reference Manual

Embedded Flash memory (FLASH)
Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected, but two
errors detection is not supported.
When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared. If
this is not the desired behavior, the user must reset the cache.
3.3.4

FLASH read access latency

To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the
frequency of the Flash (HCLK) memory clock and the internal voltage range of the device
V . Refer to
CORE
correspondence between wait states and Flash memory clock frequency.

Table 12. Number of wait states according to Flash memory clock (HCLK) frequency

Wait states (WS)
0 WS (1 HCLK cycles)
1 WS (2 HCLK cycles)
2 WS (3 HCLK cycles)
After power reset, the HCLK clock frequency is 16 MHz in Range 1 and 0 wait state (WS) is
configured in the FLASH_ACR register.
When wakeup from Standby, the HCLK clock frequency is 16 MHz in Range 1 and 0 wait
state (WS) is configured in the FLASH_ACR register.
When changing the Flash memory clock frequency or Range, the following software
sequences must be applied in order to tune the number of wait states needed to access the
Flash memory:
Increasing the CPU frequency
1. Program the new number of wait states to the LATENCY bits of the
control register
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading back the LATENCY bits of the
(FLASH_ACR), and wait until the programmed new number is read.
3. Modify the system cock source by writing the SW bits of the RCC_CFGR register.
4. If needed, modify the core clock prescaler by writing the HPRE bits of RCC_CFGR
register.
5. Optionally, check that the new system clock source or/and the new core clock prescaler
value is/are taken into account by reading the clock source status (SWS bits) of the
RCC_CFGR register, or/and the AHB prescaler value (HPREF bit), of the RCC_CFGR
register.
72/1390
FLASH access control register (FLASH_ACR)
Section 4.1.4: Dynamic voltage scaling
(LATENCY)
(FLASH_ACR).
V Range 1
CORE
≤ 24
≤ 48
≤ 64
RM0444 Rev 5
according to the
management. Table 12
HCLK (MHz)
V Range 2
CORE
≤ 8
≤ 16
-
FLASH access
FLASH access control register
RM0444
shows the