Hsw (Head-Switch) Timing Generator; Overview; Block Diagram - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

HSW (Head-switch) Timing Generator

The HSW timing generator consists of a 5-bit DFG counter, a 16-bit timer counter, a matching

circuit, and two 31-bit 10-stage FIFOs.

The 5-bit counter counts the DFG pulses following a DPG pulse. Each of them determines the

timing to reset the 16-bit timer counter for each field. The 16-bit timer counter is a timer clocked

by a φ s/4 clock source, and can be used as a programmable pattern generator (PPG) as well as a

free-running counter (FRC). If used as a free-running counter, it is cleared by overflow of the 19-

bit FRC. Accordingly, two FRCs operate synchronously. The matching circuit compares the

timing data in the most significant 16 bits of FIFO with the 16-bit timer counter, and controls the

output of the pattern data set in the least significant 15 bits of FIFO.

Figure 26.22 shows a block diagram of the HSW timing generator.

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